Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Mark Brown
On Fri, Jan 17, 2014 at 07:44:02PM +0100, Florian Meier wrote: > On 01/17/2014 07:33 PM, Mark Brown wrote: > > Setting it to false increases power consumption since the device is > > kept more powered on when idle but reduces startup time from idle. For > > digital only devices like the wm8804 th

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Florian Meier
On 01/17/2014 07:33 PM, Mark Brown wrote: > On Fri, Jan 17, 2014 at 07:06:24PM +0100, Florian Meier wrote: >> > Intentionally off-list? Oh no - I am sorry! >> If I remember correctly the error was >> "codec can not start from non-off bias with idle_bias_off==true" > >> I think the solution is ju

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Daniel Matuschek
The idle_bias_off should not be part of this patch. I will check this again. Am 17.01.2014 um 18:59 schrieb Mark Brown : > On Fri, Jan 17, 2014 at 05:43:14PM +0100, Florian Meier wrote: >> I have tested your patch. >> There is a (non blocking) error message regarding .idle_bias_off, but I >> assu

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Mark Brown
On Fri, Jan 17, 2014 at 05:43:14PM +0100, Florian Meier wrote: > I have tested your patch. > There is a (non blocking) error message regarding .idle_bias_off, but I > assume that should not have something to do with your patch. Can we just > set idle_bias_off to false here? What is the error messa

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Florian Meier
I have tested your patch. There is a (non blocking) error message regarding .idle_bias_off, but I assume that should not have something to do with your patch. Can we just set idle_bias_off to false here? Otherwise, it looks good to me. On 01/14/2014 08:34 PM, Daniel Matuschek wrote: > WM8804 can

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Mark Brown
On Tue, Jan 14, 2014 at 08:34:10PM +0100, Daniel Matuschek wrote: > WM8804 can run with PLL frequencies of 256xfs and 128xfs for > most sample rates. At 192kHz only 128xfs is supported. The > existing driver selects 128xfs automatically for some lower This patch doesn't apply against current code

RE: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Dimitris Papastamos
> Charles (or someone else from Wolfson), you commented on previous > versions of this - are you still OK with it? Looks good to me. Privacy & Confidentiality Notice - This message and any attachments contain privileged and confidential information

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Charles Keepax
On Tue, Jan 14, 2014 at 08:34:10PM +0100, Daniel Matuschek wrote: > WM8804 can run with PLL frequencies of 256xfs and 128xfs for > most sample rates. At 192kHz only 128xfs is supported. The > existing driver selects 128xfs automatically for some lower > samples rates. By using an additional mclk_di

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-16 Thread Mark Brown
On Tue, Jan 14, 2014 at 08:34:10PM +0100, Daniel Matuschek wrote: > WM8804 can run with PLL frequencies of 256xfs and 128xfs for > most sample rates. At 192kHz only 128xfs is supported. The > existing driver selects 128xfs automatically for some lower Charles (or someone else from Wolfson), you co

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-13 Thread Charles Keepax
On Sun, Jan 12, 2014 at 10:11:25PM +0100, Daniel Matuschek wrote: > Signed-off-by: Daniel Matuschek > > After some discussions of the patch last week, here is a new version. > Simply reducing the post_table did not work, as for some frequencies > both settings (MCLKDIV=0 and MCLKDIV=1) are neede

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-13 Thread Florian Meier
On 01/12/2014 10:11 PM, Daniel Matuschek wrote: > Signed-off-by: Daniel Matuschek > > After some discussions of the patch last week, here is a new version. > Simply reducing the post_table did not work, as for some frequencies > both settings (MCLKDIV=0 and MCLKDIV=1) are needed (e.g. 96 and 192k