On Monday 07 May 2007, Grant Likely wrote:
> Tested on Xilinx Virtex ppc405, Katmai 440SPe, and Microblaze
>
> Signed-off-by: Grant Likely <[EMAIL PROTECTED]>
Acked-by: Stefan Roese <[EMAIL PROTECTED]>
Best regards,
Stefan
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On 5/2/07, Andrew Morton <[EMAIL PROTECTED]> wrote:
On Wed, 2 May 2007 00:43:16 -0600 Grant Likely <[EMAIL PROTECTED]> wrote:
> + * To Do:
> + *- Add FPGA configuration control interface.
> + *- Request major number from lanana
> + *- Add legacy device geometry ioctl
> + */
Swoon.
On May 2 2007 00:45, Andrew Morton wrote:
>> +static void ace_identin_8(struct ace_device *ace)
>> +{
>> +void* r = ace->baseaddr + 0x40;
>> +int i = ACE_FIFO_SIZE/2;
>> +while (i--)
>> +#if defined(__BIG_ENDIAN)
>> +*ace->data_ptr++ = (in_8(r)) | (in_8(r+1)<<8);
>> +#else
On Wed, 2 May 2007 00:43:16 -0600 Grant Likely <[EMAIL PROTECTED]> wrote:
> Tested on Xilinx Virtex ppc405, Katmai 440SPe, and Microblaze
>
> ...
>
> + * The SystemACE chip is designed to configure FPGAs by loading an FPGA
> + * bitstream from a file on a CF card and squirting it into FPGAs conn
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