>> My apologies, the e-mail editor was not configured properly.
>> CC'ed to relevant maintainers and reposting once again with proper
>> formatting.
>>
>> Since 16 bit half word exchange was not there and MCS based qspinlock
>> by Waiman's xchg_tail() requires an atomic exchange on a half word,
On Thu, Aug 20, 2015 at 07:40:44AM +0100, Sarbojit Ganguly wrote:
> My apologies, the e-mail editor was not configured properly.
> CC'ed to relevant maintainers and reposting once again with proper formatting.
>
> Since 16 bit half word exchange was not there and MCS based qspinlock
> by Waiman's
y", "cc");
+ break;
+#endif
case 4:
asm volatile("@ __xchg4 "
"1: ldrex %0, [%3] "
Regards,
Sarbojit
--- Original Message ---
Sender : Russell King - ARM Linux
Date : Aug 20, 2015 13:49 (GMT+05:30)
T
break;
+#endif
case 4:
asm volatile("@ __xchg4\n"
"1: ldrex %0, [%3]\n"
Regards,
Sarbojit
--- Original Message ---
Sender : Catalin Marinas
Date : Aug 19, 2015 21:43 (GMT+05:30)
Title : Re: [PATCH] arm: Adding supp
On Tue, Aug 18, 2015 at 09:17:53AM +0100, Sarbojit Ganguly wrote:
>
>
> Since 16 bit half word exchange was not there and MCS based qspinlock by
> Waiman's xchg_tail() requires an atomic exchange on a half word, here is a
> small modification to __xchg() code to support the exchange.
> ARMv6 an
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