Am Freitag, 3. Mai 2019, 23:22:08 CEST schrieb Douglas Anderson:
> At boot time, my rk3288-veyron devices yell with 8 lines that look
> like this:
> [0.00] rockchip_mmc_get_phase: invalid clk rate
>
> This is because the clock framework at clk_register() time tries to
> get the phase but
Quoting Douglas Anderson (2019-05-03 14:22:08)
> At boot time, my rk3288-veyron devices yell with 8 lines that look
> like this:
> [0.00] rockchip_mmc_get_phase: invalid clk rate
>
> This is because the clock framework at clk_register() time tries to
> get the phase but we don't have a p
Am Freitag, 3. Mai 2019, 23:22:08 CEST schrieb Douglas Anderson:
> At boot time, my rk3288-veyron devices yell with 8 lines that look
> like this:
> [0.00] rockchip_mmc_get_phase: invalid clk rate
>
> This is because the clock framework at clk_register() time tries to
> get the phase but
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