From: Arnd Bergmann
Date: Thu, 22 Jan 2015 11:18:50 +0100
> I see. In this case, I think merging your new driver is not a good idea:
+1
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On Thursday 22 January 2015 00:20:59 wstep...@codeaurora.org wrote:
> > Right. For review purposes, I think it would be helpful to split this
> > huge patch into several steps then:
> >
> > - add a base driver
> > - add the overlay interface
> > - add the nss driver
> >
> > Ideally more of them.
>
> Right. For review purposes, I think it would be helpful to split this
> huge patch into several steps then:
>
> - add a base driver
> - add the overlay interface
> - add the nss driver
>
> Ideally more of them.
The nss-drv driver is open sourced but we are currently not planning to
upstream to l
On Monday 19 January 2015 21:58:09 wstep...@codeaurora.org wrote:
> > On Thursday 15 January 2015 08:12:51 wstep...@codeaurora.org wrote:
> >
> >> The nss-gmac driver is designed to work standalone or with the nss-drv
> >> driver so the switchable data plane overlay was implemented. When it
> >> wo
> On Thursday 15 January 2015 08:12:51 wstep...@codeaurora.org wrote:
>>
>> The nss-gmac driver is for the internal GMAC IP in the Qualcomm IPQ806x
>> SoC. There are 2 ARM cores and 2 NSS cores inside the IPQ806x SoC. The
>> main purpose of these NSS cores is to offload the networking stack from
>>
On Thu, 8 Jan 2015 14:03:46 -0800
Stephen Wang wrote:
> +static int32_t nss_gmac_setup_tx_desc_queue(struct nss_gmac_dev *gmacdev,
> + struct device *dev,
> + uint32_t no_of_desc,
> +
On Thu, 8 Jan 2015 14:03:46 -0800
Stephen Wang wrote:
> + struct nss_gmac_data_plane_ops *data_plane_ops;
> + /* ops to send messages to nss-drv*/
This should be a const pointer.
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On Thu, 8 Jan 2015 14:03:46 -0800
Stephen Wang wrote:
> + uint32_t rx_bytes; /**< Number of RX bytes */
> + uint32_t rx_packets;/**< Number of RX packets */
32 bit packet stats are a problem with lots of traffic.
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On Thursday 15 January 2015 08:12:51 wstep...@codeaurora.org wrote:
>
> The nss-gmac driver is for the internal GMAC IP in the Qualcomm IPQ806x
> SoC. There are 2 ARM cores and 2 NSS cores inside the IPQ806x SoC. The
> main purpose of these NSS cores is to offload the networking stack from
> the A
Hi Arnd, Francois
The nss-gmac driver is for the internal GMAC IP in the Qualcomm IPQ806x
SoC. There are 2 ARM cores and 2 NSS cores inside the IPQ806x SoC. The
main purpose of these NSS cores is to offload the networking stack from
the ARM cores to achieve high performance at routing/ipsec..etc w
On Thu, Jan 08, 2015 at 10:03:46PM +, Stephen Wang wrote:
> This driver adds support for the internal GMACs on IPQ806x SoCs.
> It supports the device-tree and will register up to 4 ethernet
> interfaces.
>
> Signed-off-by: Stephen Wang
> ---
> drivers/net/ethernet/atheros/Kconfig
Stephen Wang :
> This driver adds support for the internal GMACs on IPQ806x SoCs.
> It supports the device-tree and will register up to 4 ethernet
> interfaces.
>
> Signed-off-by: Stephen Wang
> ---
[...]
> +/*
> + * NSS GMAC data plane ops, default would be slowpath and can be override by
> + *
On Thursday 08 January 2015 14:03:46 Stephen Wang wrote:
> This driver adds support for the internal GMACs on IPQ806x SoCs.
> It supports the device-tree and will register up to 4 ethernet
> interfaces.
>
> Signed-off-by: Stephen Wang
Just a very brief review here. The driver is far too long to
On Thu, 2015-01-08 at 14:03 -0800, Stephen Wang wrote:
> This driver adds support for the internal GMACs on IPQ806x SoCs.
> It supports the device-tree and will register up to 4 ethernet
> interfaces.
Trivial:
You might try running the code through checkpatch.
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