Re: [PATCH] irqchip/gicv3: Add support for Range Selector (RS) feature

2017-09-16 Thread Shanker Donthineni
Hi Marc, On 09/16/2017 01:14 PM, Marc Zyngier wrote: > On Fri, Sep 15 2017 at 10:08:56 am BST, Shanker Donthineni > wrote: > > Hi Shanker, > >> A new feature Range Selector (RS) has been added to GIC specification >> in order to support more than 16 CPUs at affinity level 0. New fields >> are

Re: [PATCH] irqchip/gicv3: Add support for Range Selector (RS) feature

2017-09-16 Thread Marc Zyngier
On Fri, Sep 15 2017 at 10:08:56 am BST, Shanker Donthineni wrote: Hi Shanker, > A new feature Range Selector (RS) has been added to GIC specification > in order to support more than 16 CPUs at affinity level 0. New fields > are introduced in SGI system registers (ICC_SGI0R_EL1, ICC_SGI1R_EL1 >