Re: [PATCH] mtd: spi-nor: Fix 3-or-4 address byte mode logic

2020-10-06 Thread Joel Stanley
On Thu, 1 Oct 2020 at 22:23, Bert Vermeulen wrote: > > On 10/1/20 8:34 AM, Pratyush Yadav wrote: > > So using an address width of 4 here is not necessarily the right thing > > to do. This change would break SMPT parsing for all flashes that use > > 3-byte addressing by default because SMPT parsing

Re: [PATCH] mtd: spi-nor: Fix 3-or-4 address byte mode logic

2020-10-06 Thread Pratyush Yadav
On 06/10/20 11:19AM, tudor.amba...@microchip.com wrote: > On 10/6/20 2:03 PM, Tudor Ambarus - M18064 wrote: > > On 10/1/20 9:34 AM, Pratyush Yadav wrote: > >> So using an address width of 4 here is not necessarily the right thing > >> to do. This change would break SMPT parsing for all flashes that

Re: [PATCH] mtd: spi-nor: Fix 3-or-4 address byte mode logic

2020-10-06 Thread Tudor.Ambarus
On 10/6/20 2:03 PM, Tudor Ambarus - M18064 wrote: > On 10/1/20 9:34 AM, Pratyush Yadav wrote: >> So using an address width of 4 here is not necessarily the right thing >> to do. This change would break SMPT parsing for all flashes that use >> 3-byte addressing by default because SMPT parsing can in

Re: [PATCH] mtd: spi-nor: Fix 3-or-4 address byte mode logic

2020-10-06 Thread Tudor.Ambarus
On 10/1/20 9:34 AM, Pratyush Yadav wrote: > So using an address width of 4 here is not necessarily the right thing > to do. This change would break SMPT parsing for all flashes that use > 3-byte addressing by default because SMPT parsing can involve register > reads/writes. One such device is the C

RE: [PATCH] mtd: spi-nor: Fix 3-or-4 address byte mode logic

2020-10-04 Thread David Laight
From: Bert Vermeulen > Sent: 04 October 2020 22:12 > > On 10/2/20 9:50 AM, David Laight wrote: > > From: Bert Vermeulen > >> The SoCs I'm dealing with have an SPI_ADDR_SEL pin, indicating whether it > >> should be in 3 or 4-byte mode. The vendor's hacked-up U-Boot sets the mode > >> accordingly, a

Re: [PATCH] mtd: spi-nor: Fix 3-or-4 address byte mode logic

2020-10-04 Thread Bert Vermeulen
On 10/2/20 9:50 AM, David Laight wrote: > From: Bert Vermeulen >> The SoCs I'm dealing with have an SPI_ADDR_SEL pin, indicating whether it >> should be in 3 or 4-byte mode. The vendor's hacked-up U-Boot sets the mode >> accordingly, as does their BSP. It seems to me like a misfeature, and I want >

RE: [PATCH] mtd: spi-nor: Fix 3-or-4 address byte mode logic

2020-10-02 Thread David Laight
From: Bert Vermeulen > Sent: 01 October 2020 23:23 > > On 10/1/20 8:34 AM, Pratyush Yadav wrote: > > So using an address width of 4 here is not necessarily the right thing > > to do. This change would break SMPT parsing for all flashes that use > > 3-byte addressing by default because SMPT parsing

Re: [PATCH] mtd: spi-nor: Fix 3-or-4 address byte mode logic

2020-10-01 Thread Bert Vermeulen
On 10/1/20 8:34 AM, Pratyush Yadav wrote: So using an address width of 4 here is not necessarily the right thing to do. This change would break SMPT parsing for all flashes that use 3-byte addressing by default because SMPT parsing can involve register reads/writes. One such device is the Cypress

Re: [PATCH] mtd: spi-nor: Fix 3-or-4 address byte mode logic

2020-10-01 Thread Tudor.Ambarus
On 10/1/20 9:34 AM, Pratyush Yadav wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > Hi, > > On 01/10/20 01:56AM, Bert Vermeulen wrote: >> Flash chips that announce BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 capability >> get an addr_width of 3. This

Re: [PATCH] mtd: spi-nor: Fix 3-or-4 address byte mode logic

2020-09-30 Thread Pratyush Yadav
Hi, On 01/10/20 01:56AM, Bert Vermeulen wrote: > Flash chips that announce BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 capability > get an addr_width of 3. This breaks when the flash chip is actually > larger than 16MB, since that requires a 4-byte address. The MX25L25635F > does exactly this, breaking anyth