* Roger Quadros [150731 03:24]:
>
> One more observation I've had is that using irqchip modelling for
> the 2 NAND events causes a performance impact.
>
> Using mtd_oobtest I see the following on dra7-evm
>
> 1) v4.2-rc4 with prefetch-polled (no IRQs used)
> mtd_speedtest: eraseblock write spee
On 29/07/15 15:06, Roger Quadros wrote:
> Tony,
>
> On 13/07/15 15:40, Tony Lindgren wrote:
>> * Roger Quadros [150713 03:07]:
>>> Tony,
>>>
>>> On 13/07/15 10:10, Tony Lindgren wrote:
* Roger Quadros [150710 05:26]:
> Since the Interrupt Events are used only by the NAND driver,
> t
On 29/07/15 18:26, nick wrote:
>
>
> On 2015-07-29 11:12 AM, Roger Quadros wrote:
>> On 29/07/15 17:08, nick wrote:
>>>
>>>
>>> On 2015-07-29 09:52 AM, Roger Quadros wrote:
On 29/07/15 15:13, nick wrote:
>
>
> On 2015-07-29 08:06 AM, Roger Quadros wrote:
>> Tony,
>>
>
On 29/07/15 17:08, nick wrote:
>
>
> On 2015-07-29 09:52 AM, Roger Quadros wrote:
>> On 29/07/15 15:13, nick wrote:
>>>
>>>
>>> On 2015-07-29 08:06 AM, Roger Quadros wrote:
Tony,
On 13/07/15 15:40, Tony Lindgren wrote:
> * Roger Quadros [150713 03:07]:
>> Tony,
>>
On 29/07/15 15:13, nick wrote:
>
>
> On 2015-07-29 08:06 AM, Roger Quadros wrote:
>> Tony,
>>
>> On 13/07/15 15:40, Tony Lindgren wrote:
>>> * Roger Quadros [150713 03:07]:
Tony,
On 13/07/15 10:10, Tony Lindgren wrote:
> * Roger Quadros [150710 05:26]:
>> Since the Interr
Tony,
On 13/07/15 15:40, Tony Lindgren wrote:
> * Roger Quadros [150713 03:07]:
>> Tony,
>>
>> On 13/07/15 10:10, Tony Lindgren wrote:
>>> * Roger Quadros [150710 05:26]:
Since the Interrupt Events are used only by the NAND driver,
there is no point in managing the Interrupt registers
On 13/07/15 16:32, nick wrote:
>
>
> On 2015-07-13 09:21 AM, Roger Quadros wrote:
>> On 13/07/15 16:15, nick wrote:
>>>
>>>
>>> On 2015-07-13 09:12 AM, Roger Quadros wrote:
On 13/07/15 16:03, nick wrote:
>
>
> On 2015-07-13 09:01 AM, Tony Lindgren wrote:
>> * nick [150713 05
On 13/07/15 16:15, nick wrote:
>
>
> On 2015-07-13 09:12 AM, Roger Quadros wrote:
>> On 13/07/15 16:03, nick wrote:
>>>
>>>
>>> On 2015-07-13 09:01 AM, Tony Lindgren wrote:
* nick [150713 05:54]:
> On 2015-07-13 08:40 AM, Tony Lindgren wrote:
>> * Roger Quadros [150713 03:07]:
On 13/07/15 16:03, nick wrote:
>
>
> On 2015-07-13 09:01 AM, Tony Lindgren wrote:
>> * nick [150713 05:54]:
>>> On 2015-07-13 08:40 AM, Tony Lindgren wrote:
* Roger Quadros [150713 03:07]:
> What is the best map we should use for irqchip?
> Some Socs have 4 WAIT pins, some h
* nick [150713 05:54]:
> On 2015-07-13 08:40 AM, Tony Lindgren wrote:
> > * Roger Quadros [150713 03:07]:
> >
> >> What is the best map we should use for irqchip?
> >> Some Socs have 4 WAIT pins, some have 3 and some have 2.
> >>
> >> Should we start with 0,1,2, for the wait pins and use the ne
* Roger Quadros [150713 03:07]:
> Tony,
>
> On 13/07/15 10:10, Tony Lindgren wrote:
> > * Roger Quadros [150710 05:26]:
> >> Since the Interrupt Events are used only by the NAND driver,
> >> there is no point in managing the Interrupt registers
> >> in the GPMC driver and complicating it with ir
Tony,
On 13/07/15 10:10, Tony Lindgren wrote:
> * Roger Quadros [150710 05:26]:
>> Since the Interrupt Events are used only by the NAND driver,
>> there is no point in managing the Interrupt registers
>> in the GPMC driver and complicating it with irqchip modeling.
>
> I don't think it's a good
* Roger Quadros [150710 05:26]:
> Since the Interrupt Events are used only by the NAND driver,
> there is no point in managing the Interrupt registers
> in the GPMC driver and complicating it with irqchip modeling.
I don't think it's a good idea to allow external drivers to
tinker directly with G
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