On Tue, Mar 21, 2017 at 03:26:36PM +, Lorenzo Pieralisi wrote:
> I assumed that in plain terms, the difference between MT_DEVICE and
> MT_UNCACHED is write posting (aka bufferable) behaviour (across CPU
> architecture versions) and that does not affect write ordering rules.
Having looked it up
Hi Russell,
On Mon, Mar 20, 2017 at 04:43:55PM +, Russell King - ARM Linux wrote:
> On Mon, Feb 27, 2017 at 03:14:16PM +, Lorenzo Pieralisi wrote:
> > The PCI bus specifications (rev 3.0, 3.2.5 "Transaction Ordering
> > and Posting") define rules for PCI configuration space transactions
>
On Mon, Feb 27, 2017 at 03:14:16PM +, Lorenzo Pieralisi wrote:
> The PCI bus specifications (rev 3.0, 3.2.5 "Transaction Ordering
> and Posting") define rules for PCI configuration space transactions
> ordering and posting, that state that configuration writes have to
> be non-posted transactio
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