On Thu, Mar 17, 2016 at 11:58:05AM +0100, Michal Suchanek wrote:
> On 17 March 2016 at 08:27, Maxime Ripard
> > You're mixing two things up: the fact that we can't do more than the
> > FIFO length in PIO and that we're missing DMA support. We have patches
> > to address both, and there's no depede
On Thu, Mar 10, 2016 at 10:01:04AM +0100, Michal Suchanek wrote:
> Hello,
>
> On 6 March 2016 at 22:42, Maxime Ripard
> wrote:
> > On Fri, Feb 26, 2016 at 01:51:51PM +0100, Michal Suchanek wrote:
>
> >> Besides this non-technical objection there were multiple technical
> >> objections.
> >>
> >>
On Thu, Mar 17, 2016 at 12:54:08PM +0100, Michal Suchanek wrote:
> On 17 March 2016 at 12:43, Mark Brown wrote:
> > On Thu, Mar 17, 2016 at 11:58:05AM +0100, Michal Suchanek wrote:
> >> On 17 March 2016 at 08:27, Maxime Ripard
> >
> >> > You're mixing two things up: the fact that we can't do more
On 17 March 2016 at 12:43, Mark Brown wrote:
> On Thu, Mar 17, 2016 at 11:58:05AM +0100, Michal Suchanek wrote:
>> On 17 March 2016 at 08:27, Maxime Ripard
>
>> > You're mixing two things up: the fact that we can't do more than the
>> > FIFO length in PIO and that we're missing DMA support. We hav
On 17 March 2016 at 08:27, Maxime Ripard
wrote:
> On Thu, Mar 10, 2016 at 10:01:04AM +0100, Michal Suchanek wrote:
>> Hello,
>>
>> On 6 March 2016 at 22:42, Maxime Ripard
>> wrote:
>> > On Fri, Feb 26, 2016 at 01:51:51PM +0100, Michal Suchanek wrote:
>>
>> >> Besides this non-technical objection
On Thu, Mar 17, 2016 at 12:54:08PM +0100, Michal Suchanek wrote:
> That's what the driver does. The discussion revolves around the fact
> that the driver does not attempt to work (even for very short
> transfers) when the DMA channels are not configured and just bails
> out. AFAICT the channels ar
On Fri, Mar 18, 2016 at 09:23:10PM +0100, Maxime Ripard wrote:
> On Thu, Mar 17, 2016 at 12:54:08PM +0100, Michal Suchanek wrote:
> > Very few device drivers would work with 63byte transfers only and the
> > code for manually driving the CS line in case the DMA engine fails to
> > configure will n
Hello,
On 6 March 2016 at 22:42, Maxime Ripard
wrote:
> On Fri, Feb 26, 2016 at 01:51:51PM +0100, Michal Suchanek wrote:
>> Besides this non-technical objection there were multiple technical
>> objections.
>>
>> IIRC one was that the driver does not handle the case when the DMA
>> channels are n
On Fri, Feb 26, 2016 at 01:51:51PM +0100, Michal Suchanek wrote:
> Hello,
>
> On 26 February 2016 at 13:25, Mark Brown wrote:
> > On Fri, Feb 26, 2016 at 07:56:56AM +0200, Priit Laes wrote:
> >> From: Emilio López
> >>
> >> This patch adds support for 64 byte or bigger transfers on the
> >> sun4
Hello,
On 26 February 2016 at 13:25, Mark Brown wrote:
> On Fri, Feb 26, 2016 at 07:56:56AM +0200, Priit Laes wrote:
>> From: Emilio López
>>
>> This patch adds support for 64 byte or bigger transfers on the
>> sun4i SPI controller. Said transfers will be performed via DMA.
>>
>> Signed-off-by:
On Fri, Feb 26, 2016 at 07:56:56AM +0200, Priit Laes wrote:
> From: Emilio López
>
> This patch adds support for 64 byte or bigger transfers on the
> sun4i SPI controller. Said transfers will be performed via DMA.
>
> Signed-off-by: Emilio López
> Tested-by: Michal Suchanek
> Tested-by: Priit
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