On Thu, Aug 29, 2013 at 11:36 AM, Sonic Zhang wrote:
> On Thu, Aug 29, 2013 at 4:19 PM, Linus Walleij
> wrote:
>> So splitting each block into a separate pin control device is definately
>> one way to skin the cat.
>>
>> The ux500 would then have 9 pin controller instances (after a
>> big fat
On Thu, Aug 29, 2013 at 11:31 AM, Sonic Zhang wrote:
> On Thu, Aug 29, 2013 at 4:12 PM, Linus Walleij
> wrote:
>> This is similar to the situation in the pinctrl-nomadik.c driver,
>> where the pinctrl portions wait for the GPIO devices to instantiate
>> before proceeding to probe "on top" of
On Thu, Aug 29, 2013 at 11:31 AM, Sonic Zhang sonic@gmail.com wrote:
On Thu, Aug 29, 2013 at 4:12 PM, Linus Walleij linus.wall...@linaro.org
wrote:
This is similar to the situation in the pinctrl-nomadik.c driver,
where the pinctrl portions wait for the GPIO devices to instantiate
On Thu, Aug 29, 2013 at 11:36 AM, Sonic Zhang sonic@gmail.com wrote:
On Thu, Aug 29, 2013 at 4:19 PM, Linus Walleij linus.wall...@linaro.org
wrote:
So splitting each block into a separate pin control device is definately
one way to skin the cat.
The ux500 would then have 9 pin
Hi Linus,
On Thu, Aug 29, 2013 at 4:19 PM, Linus Walleij wrote:
> On Thu, Aug 22, 2013 at 10:48 PM, Stephen Warren
> wrote:
>> On 08/22/2013 01:07 AM, Sonic Zhang wrote:
>>>
>>> There are 6 to 9 GPIO HW blocks in one Blackfin SoC. Function
>>> pinmux_enable_setting() in current pinctrl
Hi Linus,
On Thu, Aug 29, 2013 at 4:12 PM, Linus Walleij wrote:
> On Thu, Aug 22, 2013 at 9:07 AM, Sonic Zhang wrote:
>
>> There are 6 to 9 GPIO HW blocks in one Blackfin SoC. Function
>> pinmux_enable_setting() in current pinctrl framework assumes the
>> function mux setting of one peripheral
Hi Stephen,
On Wed, Aug 28, 2013 at 10:23 PM, Stephen Warren wrote:
> On 08/27/2013 09:56 PM, Sonic Zhang wrote:
>> Hi Stephen,
>>
>> On Wed, Aug 28, 2013 at 5:39 AM, Stephen Warren
>> wrote:
>>> On 08/27/2013 03:30 AM, Sonic Zhang wrote:
Hi Stephen,
On Fri, Aug 23, 2013 at 4:48
Hi Linus,
On Thu, Aug 29, 2013 at 4:02 PM, Linus Walleij wrote:
> On Wed, Aug 21, 2013 at 8:30 AM, Sonic Zhang wrote:
>
>> From: Sonic Zhang
>>
>> The new ADI GPIO2 controller was introduced since the BF548 and BF60x
>> processors. It differs a lot from the old one on BF5xx processors. So,
>>
On Thu, Aug 22, 2013 at 10:48 PM, Stephen Warren wrote:
> On 08/22/2013 01:07 AM, Sonic Zhang wrote:
>>
>> There are 6 to 9 GPIO HW blocks in one Blackfin SoC. Function
>> pinmux_enable_setting() in current pinctrl framework assumes the
>> function mux setting of one peripheral pin group is
On Thu, Aug 22, 2013 at 9:07 AM, Sonic Zhang wrote:
> There are 6 to 9 GPIO HW blocks in one Blackfin SoC. Function
> pinmux_enable_setting() in current pinctrl framework assumes the
> function mux setting of one peripheral pin group is configured in one
> pinctrl device. But, the function mux
On Thu, Aug 22, 2013 at 9:07 AM, Sonic Zhang wrote:
> Is it possible that 2 and more pinctrl devices are on the same SoC? Or
> do we always assume there is only one pinctrl device on one SoC?
It is possible to have N pinctrl devices on the same SoC, not to
mention the whole system. The
On Wed, Aug 21, 2013 at 8:30 AM, Sonic Zhang wrote:
> From: Sonic Zhang
>
> The new ADI GPIO2 controller was introduced since the BF548 and BF60x
> processors. It differs a lot from the old one on BF5xx processors. So,
> create a pinctrl driver under the pinctrl framework.
(...)
The v3 is a
On Wed, Aug 21, 2013 at 8:30 AM, Sonic Zhang sonic@gmail.com wrote:
From: Sonic Zhang sonic.zh...@analog.com
The new ADI GPIO2 controller was introduced since the BF548 and BF60x
processors. It differs a lot from the old one on BF5xx processors. So,
create a pinctrl driver under the
On Thu, Aug 22, 2013 at 9:07 AM, Sonic Zhang sonic@gmail.com wrote:
Is it possible that 2 and more pinctrl devices are on the same SoC? Or
do we always assume there is only one pinctrl device on one SoC?
It is possible to have N pinctrl devices on the same SoC, not to
mention the whole
On Thu, Aug 22, 2013 at 9:07 AM, Sonic Zhang sonic@gmail.com wrote:
There are 6 to 9 GPIO HW blocks in one Blackfin SoC. Function
pinmux_enable_setting() in current pinctrl framework assumes the
function mux setting of one peripheral pin group is configured in one
pinctrl device. But, the
On Thu, Aug 22, 2013 at 10:48 PM, Stephen Warren swar...@wwwdotorg.org wrote:
On 08/22/2013 01:07 AM, Sonic Zhang wrote:
There are 6 to 9 GPIO HW blocks in one Blackfin SoC. Function
pinmux_enable_setting() in current pinctrl framework assumes the
function mux setting of one peripheral pin
Hi Linus,
On Thu, Aug 29, 2013 at 4:02 PM, Linus Walleij linus.wall...@linaro.org wrote:
On Wed, Aug 21, 2013 at 8:30 AM, Sonic Zhang sonic@gmail.com wrote:
From: Sonic Zhang sonic.zh...@analog.com
The new ADI GPIO2 controller was introduced since the BF548 and BF60x
processors. It
Hi Stephen,
On Wed, Aug 28, 2013 at 10:23 PM, Stephen Warren swar...@wwwdotorg.org wrote:
On 08/27/2013 09:56 PM, Sonic Zhang wrote:
Hi Stephen,
On Wed, Aug 28, 2013 at 5:39 AM, Stephen Warren swar...@wwwdotorg.org
wrote:
On 08/27/2013 03:30 AM, Sonic Zhang wrote:
Hi Stephen,
On Fri,
Hi Linus,
On Thu, Aug 29, 2013 at 4:12 PM, Linus Walleij linus.wall...@linaro.org wrote:
On Thu, Aug 22, 2013 at 9:07 AM, Sonic Zhang sonic@gmail.com wrote:
There are 6 to 9 GPIO HW blocks in one Blackfin SoC. Function
pinmux_enable_setting() in current pinctrl framework assumes the
Hi Linus,
On Thu, Aug 29, 2013 at 4:19 PM, Linus Walleij linus.wall...@linaro.org wrote:
On Thu, Aug 22, 2013 at 10:48 PM, Stephen Warren swar...@wwwdotorg.org
wrote:
On 08/22/2013 01:07 AM, Sonic Zhang wrote:
There are 6 to 9 GPIO HW blocks in one Blackfin SoC. Function
On 08/27/2013 09:56 PM, Sonic Zhang wrote:
> Hi Stephen,
>
> On Wed, Aug 28, 2013 at 5:39 AM, Stephen Warren wrote:
>> On 08/27/2013 03:30 AM, Sonic Zhang wrote:
>>> Hi Stephen,
>>>
>>> On Fri, Aug 23, 2013 at 4:48 AM, Stephen Warren
>>> wrote:
On 08/22/2013 01:07 AM, Sonic Zhang wrote:
On 08/27/2013 09:56 PM, Sonic Zhang wrote:
Hi Stephen,
On Wed, Aug 28, 2013 at 5:39 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 08/27/2013 03:30 AM, Sonic Zhang wrote:
Hi Stephen,
On Fri, Aug 23, 2013 at 4:48 AM, Stephen Warren swar...@wwwdotorg.org
wrote:
On 08/22/2013 01:07 AM,
Hi Stephen,
On Wed, Aug 28, 2013 at 5:39 AM, Stephen Warren wrote:
> On 08/27/2013 03:30 AM, Sonic Zhang wrote:
>> Hi Stephen,
>>
>> On Fri, Aug 23, 2013 at 4:48 AM, Stephen Warren
>> wrote:
>>> On 08/22/2013 01:07 AM, Sonic Zhang wrote:
Hi Stephen,
On Thu, Aug 22, 2013 at 2:45
On 08/27/2013 03:30 AM, Sonic Zhang wrote:
> Hi Stephen,
>
> On Fri, Aug 23, 2013 at 4:48 AM, Stephen Warren wrote:
>> On 08/22/2013 01:07 AM, Sonic Zhang wrote:
>>> Hi Stephen,
>>>
>>> On Thu, Aug 22, 2013 at 2:45 AM, Stephen Warren
>>> wrote:
On 08/21/2013 12:30 AM, Sonic Zhang wrote:
Hi Stephen,
On Fri, Aug 23, 2013 at 4:48 AM, Stephen Warren wrote:
> On 08/22/2013 01:07 AM, Sonic Zhang wrote:
>> Hi Stephen,
>>
>> On Thu, Aug 22, 2013 at 2:45 AM, Stephen Warren
>> wrote:
>>> On 08/21/2013 12:30 AM, Sonic Zhang wrote:
From: Sonic Zhang
The new ADI GPIO2
Hi Stephen,
On Fri, Aug 23, 2013 at 4:48 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 08/22/2013 01:07 AM, Sonic Zhang wrote:
Hi Stephen,
On Thu, Aug 22, 2013 at 2:45 AM, Stephen Warren swar...@wwwdotorg.org
wrote:
On 08/21/2013 12:30 AM, Sonic Zhang wrote:
From: Sonic Zhang
On 08/27/2013 03:30 AM, Sonic Zhang wrote:
Hi Stephen,
On Fri, Aug 23, 2013 at 4:48 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 08/22/2013 01:07 AM, Sonic Zhang wrote:
Hi Stephen,
On Thu, Aug 22, 2013 at 2:45 AM, Stephen Warren swar...@wwwdotorg.org
wrote:
On 08/21/2013 12:30 AM,
Hi Stephen,
On Wed, Aug 28, 2013 at 5:39 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 08/27/2013 03:30 AM, Sonic Zhang wrote:
Hi Stephen,
On Fri, Aug 23, 2013 at 4:48 AM, Stephen Warren swar...@wwwdotorg.org
wrote:
On 08/22/2013 01:07 AM, Sonic Zhang wrote:
Hi Stephen,
On Thu, Aug
On 08/22/2013 01:07 AM, Sonic Zhang wrote:
> Hi Stephen,
>
> On Thu, Aug 22, 2013 at 2:45 AM, Stephen Warren wrote:
>> On 08/21/2013 12:30 AM, Sonic Zhang wrote:
>>> From: Sonic Zhang
>>>
>>> The new ADI GPIO2 controller was introduced since the BF548 and BF60x
>>> processors. It differs a lot
Hi Stephen,
On Thu, Aug 22, 2013 at 2:45 AM, Stephen Warren wrote:
> On 08/21/2013 12:30 AM, Sonic Zhang wrote:
>> From: Sonic Zhang
>>
>> The new ADI GPIO2 controller was introduced since the BF548 and BF60x
>> processors. It differs a lot from the old one on BF5xx processors. So,
>> create a
Hi Stephen,
On Thu, Aug 22, 2013 at 2:45 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 08/21/2013 12:30 AM, Sonic Zhang wrote:
From: Sonic Zhang sonic.zh...@analog.com
The new ADI GPIO2 controller was introduced since the BF548 and BF60x
processors. It differs a lot from the old one on
On 08/22/2013 01:07 AM, Sonic Zhang wrote:
Hi Stephen,
On Thu, Aug 22, 2013 at 2:45 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 08/21/2013 12:30 AM, Sonic Zhang wrote:
From: Sonic Zhang sonic.zh...@analog.com
The new ADI GPIO2 controller was introduced since the BF548 and BF60x
On 08/21/2013 12:30 AM, Sonic Zhang wrote:
> From: Sonic Zhang
>
> The new ADI GPIO2 controller was introduced since the BF548 and BF60x
> processors. It differs a lot from the old one on BF5xx processors. So,
> create a pinctrl driver under the pinctrl framework.
> drivers/pinctrl/Kconfig
On 08/21/2013 12:30 AM, Sonic Zhang wrote:
From: Sonic Zhang sonic.zh...@analog.com
The new ADI GPIO2 controller was introduced since the BF548 and BF60x
processors. It differs a lot from the old one on BF5xx processors. So,
create a pinctrl driver under the pinctrl framework.
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