On 8/24/2017 1:10 PM, Adrian Hunter wrote:
On 18/08/17 08:19, Vijay Viswanath wrote:
From: Subhash Jadavani
SDCC controller reset (SW_RST) during probe may trigger power irq if
previous status of PWRCTL was either BUS_ON or IO_HIGH_V. So before we
enable the power irq interrupt in GIC (by re
On 18/08/17 08:19, Vijay Viswanath wrote:
> From: Subhash Jadavani
>
> SDCC controller reset (SW_RST) during probe may trigger power irq if
> previous status of PWRCTL was either BUS_ON or IO_HIGH_V. So before we
> enable the power irq interrupt in GIC (by registering the interrupt
> handler), we
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