On Fri, May 01, 2015 at 06:36:35PM -0700, Vikas Shivappa wrote:
> +#define X86_FEATURE_RDT ( 9*32+15) /* Resource Allocation */
> +#define X86_FEATURE_CAT_L3 (13*32 + 1) /* Cache QOS Enforcement L3 */
> + /* Cache Allocation Technology values */
> + u16 x8
On Thu, Feb 26, 2015 at 11:12:28AM -0800, Vikas Shivappa wrote:
> It would be easier to view the resources like CPUID availability
> through cgroup interface itself rather than add an other interface for
> the same.
Right, exposing that info in the same place where it is being
used/controlled make
On Thu, 26 Feb 2015, Borislav Petkov wrote:
On Thu, Feb 26, 2015 at 10:19:42AM -0800, Vikas Shivappa wrote:
This would be an indication that the System support RDT. On a system with
RDT would see a print.
intel_rdt: cbmlength: xx , CLOss:xx
Ok, so I have a capacity bitmask of length xx and
On Thu, Feb 26, 2015 at 10:19:42AM -0800, Vikas Shivappa wrote:
> This would be an indication that the System support RDT. On a system with
> RDT would see a print.
>
> intel_rdt: cbmlength: xx , CLOss:xx
Ok, so I have a capacity bitmask of length xx and yy classes of service.
And?
Are you expec
On Wed, 25 Feb 2015, Borislav Petkov wrote:
On Tue, Feb 24, 2015 at 04:42:10PM -0800, Vikas Shivappa wrote:
+
+ pr_info("cbmlength:%u,Closs: %u\n", cbm_len, maxid);
This text message needs to be much more user-friendly if it is going out
to the console unconditionally.
bit mask len
On Tue, Feb 24, 2015 at 04:42:10PM -0800, Vikas Shivappa wrote:
> >>+
> >>+ pr_info("cbmlength:%u,Closs: %u\n", cbm_len, maxid);
> >
> >This text message needs to be much more user-friendly if it is going out
> >to the console unconditionally.
> >
>
> bit mask lengh: number of CLOSids: ? . it s
On Tue, 24 Feb 2015, Borislav Petkov wrote:
On Tue, Feb 24, 2015 at 03:16:38PM -0800, Vikas Shivappa wrote:
-#define NCAPINTS 13 /* N 32-bit words worth of info */
+#define NCAPINTS 14 /* N 32-bit words worth of info */
#define NBUGINTS 1 /* N 32-bit bug fla
On Tue, Feb 24, 2015 at 03:16:38PM -0800, Vikas Shivappa wrote:
> This patch adds support for the new Cache Allocation Technology (CAT)
> feature found in future Intel Xeon processors. CAT is part of Intel
> Resource Director Technology(RDT) which enables sharing of processor
> resources. This patc
8 matches
Mail list logo