On Thu, Jan 11, 2018 at 4:36 PM, Timur Tabi wrote:
> On 01/11/2018 10:33 AM, Grant Likely wrote:
>>
>> What level of access control is implemented here? Is there access
>> control for each GPIO individually, or is it done by banks of GPIOs?
>> Just asking to make sure I understand the problem doma
On 01/11/2018 10:33 AM, Grant Likely wrote:
What level of access control is implemented here? Is there access
control for each GPIO individually, or is it done by banks of GPIOs?
Just asking to make sure I understand the problem domain.
On our ACPI system, it's specific GPIOs. Each GPIO is in
On Wed, Jan 10, 2018 at 1:37 PM, Linus Walleij wrote:
> On Wed, Jan 10, 2018 at 2:58 AM, Stephen Boyd wrote:
>
>> Some qcom platforms make some GPIOs or pins unavailable for use
>> by non-secure operating systems, and thus reading or writing the
>> registers for those pins will cause access contr
On Wed, 2018-01-10 at 08:37 -0800, Stephen Boyd wrote:
> On 01/10, Linus Walleij wrote:
> > On Wed, Jan 10, 2018 at 2:58 AM, Stephen Boyd
> > wrote:
> for the qcom driver it was all fine
> because all three concepts: irq, gpios, and pins have a one to
> one relationship.
Just a side note: While
On 01/10, Linus Walleij wrote:
> On Wed, Jan 10, 2018 at 2:58 AM, Stephen Boyd wrote:
>
> > +- ngpios-ranges:
> > + Usage: optional
> > + Value type:
> > + Definition: Tuples of GPIO ranges (base, size) indicating
> > + GPIOs available for use.
> > +
> > Plea
On Wed, Jan 10, 2018 at 2:58 AM, Stephen Boyd wrote:
> Some qcom platforms make some GPIOs or pins unavailable for use
> by non-secure operating systems, and thus reading or writing the
> registers for those pins will cause access control issues.
> Introduce a DT property to describe the set of G
On Tue, 2018-01-09 at 17:58 -0800, Stephen Boyd wrote:
> Some qcom platforms make some GPIOs or pins unavailable for use
> by non-secure operating systems, and thus reading or writing the
> registers for those pins will cause access control issues.
> Introduce a DT property to describe the set of G
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