On Tue, Aug 16, 2016 at 11:20:29PM +, Karl Beldan wrote:
> On Wed, Aug 10, 2016 at 05:23:23PM +0530, Sekhar Nori wrote:
> > On Wednesday 10 August 2016 04:49 PM, Karl Beldan wrote:
> > > On Wed, Aug 10, 2016 at 03:01:30PM +0530, Sekhar Nori wrote:
> > >> On Wednesday 10 August 2016 02:34 PM, Ka
On Wed, Aug 10, 2016 at 05:23:23PM +0530, Sekhar Nori wrote:
> On Wednesday 10 August 2016 04:49 PM, Karl Beldan wrote:
> > On Wed, Aug 10, 2016 at 03:01:30PM +0530, Sekhar Nori wrote:
> >> On Wednesday 10 August 2016 02:34 PM, Karl Beldan wrote:
> >>> On Wed, Aug 10, 2016 at 02:01:57PM +0530, Sekh
On Wednesday 10 August 2016 02:34 PM, Karl Beldan wrote:
> On Wed, Aug 10, 2016 at 02:01:57PM +0530, Sekhar Nori wrote:
>> On Tuesday 09 August 2016 10:45 PM, Karl Beldan wrote:
>>> This adds DT support for the NAND connected to the SoC AEMIF.
>>> The parameters (timings, ecc) are the same as what
On Tue, Aug 09, 2016 at 05:15:17PM +, Karl Beldan wrote:
> This adds DT support for the NAND connected to the SoC AEMIF.
> The parameters (timings, ecc) are the same as what the board ships with
> (default AEMIF timings, 1bit ECC) and improvements will be handled in
> due course.
> This passed
On Wednesday 10 August 2016 04:49 PM, Karl Beldan wrote:
> On Wed, Aug 10, 2016 at 03:01:30PM +0530, Sekhar Nori wrote:
>> On Wednesday 10 August 2016 02:34 PM, Karl Beldan wrote:
>>> On Wed, Aug 10, 2016 at 02:01:57PM +0530, Sekhar Nori wrote:
On Tuesday 09 August 2016 10:45 PM, Karl Beldan w
On Wed, Aug 10, 2016 at 03:01:30PM +0530, Sekhar Nori wrote:
> On Wednesday 10 August 2016 02:34 PM, Karl Beldan wrote:
> > On Wed, Aug 10, 2016 at 02:01:57PM +0530, Sekhar Nori wrote:
> >> On Tuesday 09 August 2016 10:45 PM, Karl Beldan wrote:
> >>> This adds DT support for the NAND connected to t
On Wed, Aug 10, 2016 at 02:01:57PM +0530, Sekhar Nori wrote:
> On Tuesday 09 August 2016 10:45 PM, Karl Beldan wrote:
> > This adds DT support for the NAND connected to the SoC AEMIF.
> > The parameters (timings, ecc) are the same as what the board ships with
> > (default AEMIF timings, 1bit ECC) a
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