On Wed, 01 Aug 2018 11:26:31 PDT (-0700), r...@kernel.org wrote:
On Wed, Aug 1, 2018 at 1:12 AM Christoph Hellwig wrote:
On Tue, Jul 31, 2018 at 04:46:30PM -0600, Rob Herring wrote:
> Perhaps this should be 'sifive,plic0'
Excepet for the fact this the old name has already been in shipping
har
On Thu, Aug 2, 2018 at 3:50 AM Christoph Hellwig wrote:
>
> On Wed, Aug 01, 2018 at 12:26:31PM -0600, Rob Herring wrote:
> > Not really my problem that they didn't follow the process and upstream
> > their binding first. But this alone is just a string identifier, so I
> > don't really care that m
On Wed, Aug 01, 2018 at 12:26:31PM -0600, Rob Herring wrote:
> Not really my problem that they didn't follow the process and upstream
> their binding first. But this alone is just a string identifier, so I
> don't really care that much. If things are really a mess, then the
> next implementations w
On Wed, Aug 1, 2018 at 1:12 AM Christoph Hellwig wrote:
>
> On Tue, Jul 31, 2018 at 04:46:30PM -0600, Rob Herring wrote:
> > Perhaps this should be 'sifive,plic0'
>
> Excepet for the fact this the old name has already been in shipping
> hardware and release of qemu and other emulators it should.
On Tue, Jul 31, 2018 at 04:46:30PM -0600, Rob Herring wrote:
> Perhaps this should be 'sifive,plic0'
Excepet for the fact this the old name has already been in shipping
hardware and release of qemu and other emulators it should.
> Normally this would have an SoC specific compatible too. Sometimes
On Wed, Jul 25, 2018 at 11:36:49AM +0200, Christoph Hellwig wrote:
> From: Palmer Dabbelt
>
> This patch adds documentation for the platform-level interrupt
> controller (PLIC) found in all RISC-V systems. This interrupt
> controller routes interrupts from all the devices in the system to each
>
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