> > > My problem with that is it's not really much different to just skipping
> > > the
> > > page table update entirely. Skipping the DSB is closer to what is done on
> > > x86, where we bound the stale entry time to the next context-switch.
> >
> > Which of the three implementations is the "th
On Thu, Dec 06, 2018 at 08:42:03PM +, Alexander Van Brunt wrote:
> > > > If we roll a TLB invalidation routine without the trailing DSB, what
> > > >sort of
> > > > performance does that get you?
> > >
> > > It is not as good. In some cases, it is really bad. Skipping the
> > > invalidate wa
> > > If we roll a TLB invalidation routine without the trailing DSB, what sort
> > >of
> > > performance does that get you?
> >
> > It is not as good. In some cases, it is really bad. Skipping the invalidate
> > was
> > the most consistent and fast implementation.
> My problem with that is it'
Hi Alex,
Thanks for running these tests and providing the in-depth analysis.
On Mon, Dec 03, 2018 at 09:20:25PM +, Alexander Van Brunt wrote:
> > If we roll a TLB invalidation routine without the trailing DSB, what sort of
> > performance does that get you?
>
> It is not as good. In some cas
> If we roll a TLB invalidation routine without the trailing DSB, what sort of
> performance does that get you?
It is not as good. In some cases, it is really bad. Skipping the invalidate was
the most consistent and fast implementation.
Methodology:
We ran 6 tests on Jetson Xavier with three dif
[Sorry to be "that person" but please can you use plain text for your mail?
This is getting really hard to follow.]
On Tue, Oct 30, 2018 at 11:17:34AM +0530, Ashish Mhetre wrote:
> On 29/10/18 4:25 PM, Will Deacon wrote:
> On Mon, Oct 29, 2018 at 02:55:58PM +0530, Ashish Mhetre wrote:
>
r Van Brunt; Sachin Nikam;
linux-kernel@vger.kernel.org
Subject: Re: [PATCH V3] arm64: Don't flush tlb while clearing the accessed bit
On Mon, Oct 29, 2018 at 02:55:58PM +0530, Ashish Mhetre wrote:
> From: Alex Van Brunt
>
> Accessed bit is used to age a page and in generi
On Mon, Oct 29, 2018 at 02:55:58PM +0530, Ashish Mhetre wrote:
> From: Alex Van Brunt
>
> Accessed bit is used to age a page and in generic implementation there is
> flush_tlb while clearing the accessed bit.
> Flushing a TLB is overhead on ARM64 as access flag faults don't get
> translation tabl
On 29/10/2018 09:25, Ashish Mhetre wrote:
> From: Alex Van Brunt
>
> Accessed bit is used to age a page and in generic implementation there is
> flush_tlb while clearing the accessed bit.
> Flushing a TLB is overhead on ARM64 as access flag faults don't get
> translation table entries cached in
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