Re: [PATCH v1 02/11] clk: mediatek: add new member to mtk_pll_data

Quoting Weiyi Lu (2018-11-19 19:51:20) > On Tue, 2018-11-13 at 08:18 -0800, Nicolas Boichat wrote: > > On Mon, Nov 5, 2018 at 10:43 PM Weiyi Lu wrote: > > > @@ -138,9 +140,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll > > > *pll, u32 pcw, > > > static void mtk_pll_calc_values(struct

Re: [PATCH v1 02/11] clk: mediatek: add new member to mtk_pll_data

On Tue, 2018-11-13 at 08:18 -0800, Nicolas Boichat wrote: > On Mon, Nov 5, 2018 at 10:43 PM Weiyi Lu wrote: > > > > From: Owen Chen > > > > 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits, > >add a variable to indicate this change and > >backward-compatible. > > 2. fmin:

Re: [PATCH v1 02/11] clk: mediatek: add new member to mtk_pll_data

On Mon, Nov 5, 2018 at 10:43 PM Weiyi Lu wrote: > > From: Owen Chen > > 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits, >add a variable to indicate this change and >backward-compatible. > 2. fmin: The pll freqency lower-bound is vary from 1GMhz to >1.5Ghz, add a var