Re: [PATCH v1 1/2] x86/power/64: Support unaligned addresses for temporary mapping

On Tue, Aug 2, 2016 at 12:55 PM, Yinghai Lu wrote: > On Tue, Aug 2, 2016 at 10:48 AM, Thomas Garnier wrote: >> On Tue, Aug 2, 2016 at 10:36 AM, Yinghai Lu wrote: >>> >>> Looks like we need to change the loop from phys address to

Re: [PATCH v1 1/2] x86/power/64: Support unaligned addresses for temporary mapping

On Tue, Aug 2, 2016 at 12:55 PM, Yinghai Lu wrote: > On Tue, Aug 2, 2016 at 10:48 AM, Thomas Garnier wrote: >> On Tue, Aug 2, 2016 at 10:36 AM, Yinghai Lu wrote: >>> >>> Looks like we need to change the loop from phys address to virtual >>> address instead. >>> to avoid the overflow. > >

Re: [PATCH v1 1/2] x86/power/64: Support unaligned addresses for temporary mapping

On Tue, Aug 2, 2016 at 10:48 AM, Thomas Garnier wrote: > On Tue, Aug 2, 2016 at 10:36 AM, Yinghai Lu wrote: >> >> Looks like we need to change the loop from phys address to virtual >> address instead. >> to avoid the overflow. something like attached.

Re: [PATCH v1 1/2] x86/power/64: Support unaligned addresses for temporary mapping

On Tue, Aug 2, 2016 at 10:48 AM, Thomas Garnier wrote: > On Tue, Aug 2, 2016 at 10:36 AM, Yinghai Lu wrote: >> >> Looks like we need to change the loop from phys address to virtual >> address instead. >> to avoid the overflow. something like attached. --- arch/x86/mm/ident_map.c | 54

Re: [PATCH v1 1/2] x86/power/64: Support unaligned addresses for temporary mapping

On Mon, Aug 1, 2016 at 5:36 PM, Rafael J. Wysocki wrote: > On Monday, August 01, 2016 10:07:59 AM Thomas Garnier wrote: >> Correctly setup the temporary mapping for hibernation. Previous >> implementation assumed the address was aligned on the PGD level. With >> KASLR memory

Re: [PATCH v1 1/2] x86/power/64: Support unaligned addresses for temporary mapping

On Mon, Aug 1, 2016 at 5:36 PM, Rafael J. Wysocki wrote: > On Monday, August 01, 2016 10:07:59 AM Thomas Garnier wrote: >> Correctly setup the temporary mapping for hibernation. Previous >> implementation assumed the address was aligned on the PGD level. With >> KASLR memory randomization

Re: [PATCH v1 1/2] x86/power/64: Support unaligned addresses for temporary mapping

On Tue, Aug 2, 2016 at 10:36 AM, Yinghai Lu wrote: > On Mon, Aug 1, 2016 at 10:07 AM, Thomas Garnier wrote: >> Correctly setup the temporary mapping for hibernation. Previous >> implementation assumed the address was aligned on the PGD level. With >>

Re: [PATCH v1 1/2] x86/power/64: Support unaligned addresses for temporary mapping

On Tue, Aug 2, 2016 at 10:36 AM, Yinghai Lu wrote: > On Mon, Aug 1, 2016 at 10:07 AM, Thomas Garnier wrote: >> Correctly setup the temporary mapping for hibernation. Previous >> implementation assumed the address was aligned on the PGD level. With >> KASLR memory randomization enabled, the

Re: [PATCH v1 1/2] x86/power/64: Support unaligned addresses for temporary mapping

On Mon, Aug 1, 2016 at 10:07 AM, Thomas Garnier wrote: > Correctly setup the temporary mapping for hibernation. Previous > implementation assumed the address was aligned on the PGD level. With > KASLR memory randomization enabled, the address is randomized on the PUD > level.

Re: [PATCH v1 1/2] x86/power/64: Support unaligned addresses for temporary mapping

On Mon, Aug 1, 2016 at 10:07 AM, Thomas Garnier wrote: > Correctly setup the temporary mapping for hibernation. Previous > implementation assumed the address was aligned on the PGD level. With > KASLR memory randomization enabled, the address is randomized on the PUD > level. This change supports

Re: [PATCH v1 1/2] x86/power/64: Support unaligned addresses for temporary mapping

On Monday, August 01, 2016 10:07:59 AM Thomas Garnier wrote: > Correctly setup the temporary mapping for hibernation. Previous > implementation assumed the address was aligned on the PGD level. With > KASLR memory randomization enabled, the address is randomized on the PUD > level. This change

Re: [PATCH v1 1/2] x86/power/64: Support unaligned addresses for temporary mapping

On Monday, August 01, 2016 10:07:59 AM Thomas Garnier wrote: > Correctly setup the temporary mapping for hibernation. Previous > implementation assumed the address was aligned on the PGD level. With > KASLR memory randomization enabled, the address is randomized on the PUD > level. This change