On Fri, Dec 22, 2017 at 06:40:04PM +0800, chen liu wrote:
> 2017-12-22 0:48 GMT+08:00 Charles Keepax :
> > On Tue, Dec 19, 2017 at 02:19:48PM +0800, chen liu wrote:
> >> 2017-12-18 19:55 GMT+08:00 Charles Keepax :
> >> > On Mon, Dec 18, 2017 at 07:32:41PM +0800, chen liu wrote:
> >> > > 2017-12-18
2017-12-22 0:48 GMT+08:00 Charles Keepax :
> On Tue, Dec 19, 2017 at 02:19:48PM +0800, chen liu wrote:
>> 2017-12-18 19:55 GMT+08:00 Charles Keepax :
>> > On Mon, Dec 18, 2017 at 07:32:41PM +0800, chen liu wrote:
>> > > 2017-12-18 17:31 GMT+08:00 Charles Keepax > > > > On Fri, Dec 15, 2017 at 09:07
On Tue, Dec 19, 2017 at 02:19:48PM +0800, chen liu wrote:
> 2017-12-18 19:55 GMT+08:00 Charles Keepax :
> > On Mon, Dec 18, 2017 at 07:32:41PM +0800, chen liu wrote:
> > > 2017-12-18 17:31 GMT+08:00 Charles Keepax > > > On Fri, Dec 15, 2017 at 09:07:15PM +0800, chen liu wrote:
> > > > > 2017-12-15
On Mon, Dec 18, 2017 at 07:32:41PM +0800, chen liu wrote:
> 2017-12-18 17:31 GMT+08:00 Charles Keepax :
>
> > On Fri, Dec 15, 2017 at 09:07:15PM +0800, chen liu wrote:
> > > 2017-12-15 0:19 GMT+08:00 Charles Keepax > >:
> > > > On Wed, Dec 13, 2017 at 08:37:30PM +0800, Chen.Liu wrote:
> According
On Fri, Dec 15, 2017 at 09:07:15PM +0800, chen liu wrote:
> 2017-12-15 0:19 GMT+08:00 Charles Keepax :
> > On Wed, Dec 13, 2017 at 08:37:30PM +0800, Chen.Liu wrote:
> When the MCLK clock frequency cannot meet the SYSCLK clock
> frequency of the wm8960 codec,we must use the PLL divider to
> generate
On Thu, Dec 14, 2017 at 03:51:51PM +, Charles Keepax wrote:
> On Thu, Dec 14, 2017 at 03:31:39PM +, Mark Brown wrote:
> > Removing set_clkdiv() would be a better thing if there were conflicts
> > here, in general we're trying to avoid uses of it.
> Ok that can probably be done as a separa
On Wed, Dec 13, 2017 at 08:37:30PM +0800, Chen.Liu wrote:
> From: "Chen.Liu"
> diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c
> index 997c446..83dd746 100644
> --- a/sound/soc/codecs/wm8960.c
> +++ b/sound/soc/codecs/wm8960.c
> @@ -1036,28 +1036,38 @@ static bool is_pll_freq_av
On Thu, Dec 14, 2017 at 03:31:39PM +, Mark Brown wrote:
> On Thu, Dec 14, 2017 at 11:56:48AM +, Charles Keepax wrote:
> > On Wed, Dec 13, 2017 at 08:37:30PM +0800, Chen.Liu wrote:
>
> > > + if (unsupported)
> > > + snd_soc_update_bits(codec, WM8960_CLOCK1, 0x6,
> > > +
On Thu, Dec 14, 2017 at 11:56:48AM +, Charles Keepax wrote:
> On Wed, Dec 13, 2017 at 08:37:30PM +0800, Chen.Liu wrote:
> > + if (unsupported)
> > + snd_soc_update_bits(codec, WM8960_CLOCK1, 0x6,
> > + WM8960_SYSCLK_DIV_2);
> > +
> Looking at this a bit m
On Wed, Dec 13, 2017 at 08:37:30PM +0800, Chen.Liu wrote:
> From: "Chen.Liu"
>
> Issue:
> MCLK=24MHZ,SYSCLOCK=12.288MHZ.
> When the 'wm8960_set_pll' function is called,the driver will
> prompted "WM8960 PLL: unsupported N = 4" error message.
> However,the value of PLLN should be 8 based on th
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