Re: [PATCH v2 2/2] clk: stm32f4: fix timeout management for pll and ready gate

2017-04-05 Thread Stephen Boyd
On 03/16, gabriel.fernan...@st.com wrote: > From: Gabriel Fernandez > > Use a classic polling to test bit ready. > And the shift of the bit ready of LSE & LSI were wrongs. > > Fixes: 861adc44d290 ("clk: stm32f4: Add LSI & LSE clocks") > > Signed-off-by: Gabriel

Re: [PATCH v2 2/2] clk: stm32f4: fix timeout management for pll and ready gate

2017-04-05 Thread Stephen Boyd
On 03/16, gabriel.fernan...@st.com wrote: > From: Gabriel Fernandez > > Use a classic polling to test bit ready. > And the shift of the bit ready of LSE & LSI were wrongs. > > Fixes: 861adc44d290 ("clk: stm32f4: Add LSI & LSE clocks") > > Signed-off-by: Gabriel Fernandez > --- Applied to