Re: [PATCH v2 3/5] clk: mediatek: Fix asymmetrical PLL enable and disable control

2020-08-10 Thread Weiyi Lu
On Wed, 2020-07-29 at 18:51 +0800, Nicolas Boichat wrote: > On Wed, Jul 29, 2020 at 4:44 PM Weiyi Lu wrote: > > > > The en_mask actually is a combination of divider enable mask > > and pll enable bit(bit0). > > Before this patch, we enabled both divider mask and bit0 in prepare(), > > but only cle

Re: [PATCH v2 3/5] clk: mediatek: Fix asymmetrical PLL enable and disable control

2020-08-10 Thread Weiyi Lu
On Wed, 2020-07-29 at 19:02 +0800, Nicolas Boichat wrote: > On Wed, Jul 29, 2020 at 6:51 PM Nicolas Boichat wrote: > > > > On Wed, Jul 29, 2020 at 4:44 PM Weiyi Lu wrote: > > > > > > The en_mask actually is a combination of divider enable mask > > > and pll enable bit(bit0). > > > Before this pat

Re: [PATCH v2 3/5] clk: mediatek: Fix asymmetrical PLL enable and disable control

2020-07-29 Thread Nicolas Boichat
On Wed, Jul 29, 2020 at 6:51 PM Nicolas Boichat wrote: > > On Wed, Jul 29, 2020 at 4:44 PM Weiyi Lu wrote: > > > > The en_mask actually is a combination of divider enable mask > > and pll enable bit(bit0). > > Before this patch, we enabled both divider mask and bit0 in prepare(), > > but only cle

Re: [PATCH v2 3/5] clk: mediatek: Fix asymmetrical PLL enable and disable control

2020-07-29 Thread Nicolas Boichat
On Wed, Jul 29, 2020 at 4:44 PM Weiyi Lu wrote: > > The en_mask actually is a combination of divider enable mask > and pll enable bit(bit0). > Before this patch, we enabled both divider mask and bit0 in prepare(), > but only cleared the bit0 in unprepare(). > Now, setting the enable register(CON0)