On Tue, Jan 09, 2018 at 01:22:12PM -0800, Stephen Boyd wrote:
> On 12/14, Will Deacon wrote:
> > On Wed, Dec 13, 2017 at 02:19:37PM -0800, Stephen Boyd wrote:
> > > The Kryo CPUs are also affected by the Falkor 1003 errata, so
> > > we need to do the same workaround on Kryo CPUs. The MIDR is
> > >
On 12/14, Will Deacon wrote:
> On Wed, Dec 13, 2017 at 02:19:37PM -0800, Stephen Boyd wrote:
> > The Kryo CPUs are also affected by the Falkor 1003 errata, so
> > we need to do the same workaround on Kryo CPUs. The MIDR is
> > slightly more complicated here, where the PART number is not
> > always
On Wed, Dec 13, 2017 at 02:19:37PM -0800, Stephen Boyd wrote:
> The Kryo CPUs are also affected by the Falkor 1003 errata, so
> we need to do the same workaround on Kryo CPUs. The MIDR is
> slightly more complicated here, where the PART number is not
> always the same when looking at all the bits f
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