On 6/19/2018 3:04 PM, Sudeep Holla wrote:
On 19/06/18 08:53, Taniya Das wrote:
On 6/18/2018 2:51 PM, Sudeep Holla wrote:
On 15/06/18 18:40, Taniya Das wrote:
On 6/15/2018 5:29 PM, Amit Kucheria wrote:
[...]
A future version of the HW engine, or more likely, a firmware
revision,
On 19/06/18 08:53, Taniya Das wrote:
>
>
> On 6/18/2018 2:51 PM, Sudeep Holla wrote:
>>
>>
>> On 15/06/18 18:40, Taniya Das wrote:
>>>
>>>
>>> On 6/15/2018 5:29 PM, Amit Kucheria wrote:
>>
>> [...]
>>
A future version of the HW engine, or more likely, a firmware
revision, will make m
On 19-06-18, 13:23, Taniya Das wrote:
> Driver code (The below representation is just for example).
> =
>
> V1
> #define ENABLE0x0
> #define LUT_V10x110
> #define PERF_V1 0x920
>
> V2
> #define LUT_V20x150
> #define PERF_V2 0x980
>
> V3
> #define L
On 6/18/2018 2:51 PM, Sudeep Holla wrote:
On 15/06/18 18:40, Taniya Das wrote:
On 6/15/2018 5:29 PM, Amit Kucheria wrote:
[...]
A future version of the HW engine, or more likely, a firmware
revision, will make more functionality available. Say, this needs
access to another register or
On 15/06/18 18:40, Taniya Das wrote:
>
>
> On 6/15/2018 5:29 PM, Amit Kucheria wrote:
[...]
>> A future version of the HW engine, or more likely, a firmware
>> revision, will make more functionality available. Say, this needs
>> access to another register or two. This will require changing t
On Fri, Jun 15, 2018 at 8:40 PM, Taniya Das wrote:
>
>
> On 6/15/2018 5:29 PM, Amit Kucheria wrote:
>>
>> On Thu, Jun 14, 2018 at 9:24 PM, Taniya Das wrote:
>>
> Sorry Sudeep I missed replying to your earlier query.
> The High level OS(HLOS) would require to access only these specific
>>>
On 15/06/18 18:40, Taniya Das wrote:
>
>
> On 6/15/2018 5:29 PM, Amit Kucheria wrote:
>> On Thu, Jun 14, 2018 at 9:24 PM, Taniya Das wrote:
>>
> Sorry Sudeep I missed replying to your earlier query.
> The High level OS(HLOS) would require to access only these specific
> registers
On 15/06/18 18:31, Taniya Das wrote:
>
>
> On 6/15/2018 6:53 PM, Sudeep Holla wrote:
>>
[...]
>>>
It should be easily extensible is what I am
trying to say. You can add more info and alter the information in the
driver with compatibles if you keep the register info as minimum
On 6/15/2018 5:29 PM, Amit Kucheria wrote:
On Thu, Jun 14, 2018 at 9:24 PM, Taniya Das wrote:
Sorry Sudeep I missed replying to your earlier query.
The High level OS(HLOS) would require to access only these specific
registers from this IP block and just mapping the whole block(huge
region)
On 6/15/2018 6:53 PM, Sudeep Holla wrote:
On 14/06/18 19:24, Taniya Das wrote:
Hello Sudeep,
Thanks for your comments.
On 6/14/2018 4:17 PM, Sudeep Holla wrote:
On 13/06/18 19:13, Taniya Das wrote:
Hello Sudeep,
Thanks for review comments.
On 6/13/2018 4:56 PM, Sudeep Holla wrote:
On 15/06/18 12:59, Amit Kucheria wrote:
> On Thu, Jun 14, 2018 at 9:24 PM, Taniya Das wrote:
>
[...]
>>
>> Yes I do understand the intent of mapping the whole register space, but as
>> per the HW specs these 3 registers would be the only ones required for now.
>> I do not think this hardware
On 14/06/18 19:24, Taniya Das wrote:
> Hello Sudeep,
>
> Thanks for your comments.
>
> On 6/14/2018 4:17 PM, Sudeep Holla wrote:
>>
>>
>> On 13/06/18 19:13, Taniya Das wrote:
>>> Hello Sudeep,
>>>
>>> Thanks for review comments.
>>>
>>> On 6/13/2018 4:56 PM, Sudeep Holla wrote:
>>
>>
On Tue, Jun 12, 2018 at 2:02 PM, Taniya Das wrote:
> Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
> SoCs. This is required for managing the cpu frequency transitions which are
> controlled by firmware.
>
> Signed-off-by: Taniya Das
> + qcom,cpufreq-fw {
> +
On Thu, Jun 14, 2018 at 9:24 PM, Taniya Das wrote:
>>> Sorry Sudeep I missed replying to your earlier query.
>>> The High level OS(HLOS) would require to access only these specific
>>> registers from this IP block and just mapping the whole block(huge
>>> region) is unnecessary from the OS point
Hello Sudeep,
Thanks for your comments.
On 6/14/2018 4:17 PM, Sudeep Holla wrote:
On 13/06/18 19:13, Taniya Das wrote:
Hello Sudeep,
Thanks for review comments.
On 6/13/2018 4:56 PM, Sudeep Holla wrote:
[...]
You are bit inconsistent on the wordings. Some places you refer this as
ha
On 13/06/18 19:13, Taniya Das wrote:
> Hello Sudeep,
>
> Thanks for review comments.
>
> On 6/13/2018 4:56 PM, Sudeep Holla wrote:
>>
>>
[...]
>> You are bit inconsistent on the wordings. Some places you refer this as
>> hardware engine. If so, please drop all references to firmware/FW. If
>
Hello Sudeep,
Thanks for review comments.
On 6/13/2018 4:56 PM, Sudeep Holla wrote:
On 12/06/18 12:02, Taniya Das wrote:
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by firmware.
On 12/06/18 12:02, Taniya Das wrote:
> Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
> SoCs. This is required for managing the cpu frequency transitions which are
> controlled by firmware.
>
> Signed-off-by: Taniya Das
> ---
> .../bindings/cpufreq/cpufreq-qcom-fw.txt
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