On Mon, 11 Jan 2021 11:31:11 PST (-0800), ati...@atishpatra.org wrote:
On Sat, Jan 9, 2021 at 12:51 PM Palmer Dabbelt wrote:
On Sun, 13 Dec 2020 17:02:19 PST (-0800), ati...@atishpatra.org wrote:
> On Wed, Nov 18, 2020 at 4:39 PM Atish Patra wrote:
>>
>> This series attempts to move the ARM64
On Sat, Jan 9, 2021 at 12:51 PM Palmer Dabbelt wrote:
>
> On Sun, 13 Dec 2020 17:02:19 PST (-0800), ati...@atishpatra.org wrote:
> > On Wed, Nov 18, 2020 at 4:39 PM Atish Patra wrote:
> >>
> >> This series attempts to move the ARM64 numa implementation to common
> >> code so that RISC-V can lever
On Sun, 13 Dec 2020 17:02:19 PST (-0800), ati...@atishpatra.org wrote:
On Wed, Nov 18, 2020 at 4:39 PM Atish Patra wrote:
This series attempts to move the ARM64 numa implementation to common
code so that RISC-V can leverage that as well instead of reimplementing
it again.
RISC-V specific bits
On Wed, Nov 18, 2020 at 4:39 PM Atish Patra wrote:
>
> This series attempts to move the ARM64 numa implementation to common
> code so that RISC-V can leverage that as well instead of reimplementing
> it again.
>
> RISC-V specific bits are based on initial work done by Greentime Hu [1] but
> modifi
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