On Friday 24 March 2017 05:06 PM, Mark Rutland wrote:
+#define SC_DJTAG_TIMEOUT_US(100 * USEC_PER_MSEC) /* 100ms */
> >How was this value chosen?
> >
> >How likely is a timeout?
>
>As explained in PATCH 7,
>
>The djtag -EBUSY in hardware is a very rare scenario, and by design
>of hardware
On Fri, Mar 24, 2017 at 04:16:25PM +0530, Anurup M wrote:
> Thanks for the review.
>
> On Tuesday 21 March 2017 09:21 PM, Mark Rutland wrote:
> >On Fri, Mar 10, 2017 at 01:28:22AM -0500, Anurup M wrote:
> >>+#define SC_DJTAG_TIMEOUT_US(100 * USEC_PER_MSEC) /* 100ms */
> >How was this value ch
Thanks for the review.
On Tuesday 21 March 2017 09:21 PM, Mark Rutland wrote:
On Fri, Mar 10, 2017 at 01:28:22AM -0500, Anurup M wrote:
From: Tan Xiaojun
The Hisilicon Djtag is an independent component which connects
with some other components in the SoC by Debug Bus. This driver
can be confi
On Fri, Mar 10, 2017 at 01:28:22AM -0500, Anurup M wrote:
> From: Tan Xiaojun
>
> The Hisilicon Djtag is an independent component which connects
> with some other components in the SoC by Debug Bus. This driver
> can be configured to access the registers of connecting components
> (like L3 cache)
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