Hi,
On Wed, Jul 02, 2014 at 02:48:17PM +0200, Arnd Bergmann wrote:
> On Wednesday 02 July 2014 11:43:25 Ivan T. Ivanov wrote:
> > > >
> > > >
> > > >> > +
> > > >> > + ranges;
> > > >> > +
> > > >> > + status = "disabled";
> > > >> > +
> > > >> > +
On Wednesday 02 July 2014 11:43:25 Ivan T. Ivanov wrote:
> > >
> > >
> > >> > +
> > >> > + ranges;
> > >> > +
> > >> > + status = "disabled";
> > >> > +
> > >> > + dwc3@1100 {
> > >> > + compatible
Hi,
On Tue, 2014-07-01 at 14:47 -0500, Rob Herring wrote:
> On Tue, Jul 1, 2014 at 1:01 PM, Andy Gross wrote:
> > On Tue, Jul 01, 2014 at 12:04:35AM -0500, Rob Herring wrote:
> >
> >
> >> > +
> >> > + ranges;
> >> > +
> >> > + status = "disabled";
On Tue, Jul 1, 2014 at 1:01 PM, Andy Gross wrote:
> On Tue, Jul 01, 2014 at 12:04:35AM -0500, Rob Herring wrote:
>
>
>
>> > +- clock-names: Should contain the following:
>> > + "core" Master/Core clock, have to be >= 125 MHz for SS
>> > + operation and
On Tue, Jul 01, 2014 at 12:04:35AM -0500, Rob Herring wrote:
> > +- clock-names: Should contain the following:
> > + "core" Master/Core clock, have to be >= 125 MHz for SS
> > + operation and >= 60MHz for HS operation
> > +
> > +Optional clocks:
> > +
On Mon, Jun 30, 2014 at 11:03 AM, Andy Gross wrote:
> From: "Ivan T. Ivanov"
Please copy the right lists and maintainers.
>
> QCOM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
> (SNPS) and HS, SS PHY's control and configuration registers.
>
> It could operate in device mode (SS, HS, F
On Jun 30, 2014, at 11:03 AM, Andy Gross wrote:
> From: "Ivan T. Ivanov"
>
> QCOM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
> (SNPS) and HS, SS PHY's control and configuration registers.
>
> It could operate in device mode (SS, HS, FS) and host
> mode (SS, HS, FS, LS).
>
> Signe
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