On 19/02/2021 19:52, Pierre-Louis Bossart wrote:
It seems you are in a different solution-space, where the codec driver
needs to notify the master of which ports it needs to use?
Correct! As Codec is the place where we have mixer controls ant it can
clearly tell which master ports should b
It seems you are in a different solution-space, where the codec driver
needs to notify the master of which ports it needs to use?
Correct! As Codec is the place where we have mixer controls ant it can
clearly tell which master ports should be used for that particular
configuration.
And that
Hi Pierre/Vinod,
On 01/02/2021 10:27, Vinod Koul wrote:
It seems you are in a different solution-space, where the codec driver
needs to notify the master of which ports it needs to use?
Correct! As Codec is the place where we have mixer controls ant it can
clearly tell which master ports should
On 25-01-21, 16:23, Srinivas Kandagatla wrote:
>
>
> On 22/01/2021 16:42, Pierre-Louis Bossart wrote:
> > > >
> > > > if you completely remove the stream and re-add it with updated
> > > > configuration things should work.
> > >
> > > That's exactly what we do currently!
> > >
> > > The update
On 22/01/2021 16:42, Pierre-Louis Bossart wrote:
if you completely remove the stream and re-add it with updated
configuration things should work.
That's exactly what we do currently!
The updated ports due to new configuration ex: for "mic capture"
dailink needs to be communicated from sl
On 22/01/2021 15:32, Pierre-Louis Bossart wrote:
Are you suggesting that we have dailink for each usecase like:
"headset capture"
"Analog MIC1 capture"
"Analog MIC2 Capture"
...
"Analog MIC4 Capture"
...
"DMIC0 capture"
"DMIC1 Capture"
"DMIC2 Capture"
...
"DMIC7 Capture"
..
"Headset Pl
No, what I was saying is that you need to define multiple streams e.g.
- headset capture (configured with or without click suppression)
- mic capture (configured with AMICs or DMICs)
- playback (or possibly different endpoint specific streams depending
on whether concurrency between endpoint i
On 1/22/21 1:05 AM, Srinivas Kandagatla wrote:
On 21/01/2021 21:30, Pierre-Louis Bossart wrote:
Am looking at intel_hw_params(). Isn't sdw_stream_add_master() called
for every dai in the dai link.
Yes, that's correct, but again a dai may use one or more ports.
if you defined each port
On 21/01/2021 21:30, Pierre-Louis Bossart wrote:
Am looking at intel_hw_params(). Isn't sdw_stream_add_master() called
for every dai in the dai link.
Yes, that's correct, but again a dai may use one or more ports.
if you defined each port as a dai, and want to call
sdw_stream_add_master(
[SLAVE]---[MASTER]
NA-Port 1: PCM
Port 1-Port 2: ADC 1 & 2
Port 2-Port 3: ADC 3 & 4
Port 3-Port 4: DMIC-0, DMIC-1, DIMC-2 , DMIC-3 and MBHC
Port 4-Port 5: DMIC-4, DMIC-5, DMIC-6 and DMIC-7
Mapping is still static however Number of ports selectio
On 21/01/2021 18:00, Pierre-Louis Bossart wrote:
On 1/21/21 9:41 AM, Srinivas Kandagatla wrote:
On 21/01/2021 14:56, Pierre-Louis Bossart wrote:
Port allocations are something like this:
RX: (Simple)
Port 1 -> HPH L/R
Port 2 -> CLASS H Amp
Port 3 -> COMP
Port 4 -> DSD.
TX: (This get
On 1/21/21 9:41 AM, Srinivas Kandagatla wrote:
On 21/01/2021 14:56, Pierre-Louis Bossart wrote:
Port allocations are something like this:
RX: (Simple)
Port 1 -> HPH L/R
Port 2 -> CLASS H Amp
Port 3 -> COMP
Port 4 -> DSD.
TX: (This get bit more complicated)
Port 1: PCM
Port 2: ADC 1 & 2
On 21/01/2021 14:56, Pierre-Louis Bossart wrote:
Port allocations are something like this:
RX: (Simple)
Port 1 -> HPH L/R
Port 2 -> CLASS H Amp
Port 3 -> COMP
Port 4 -> DSD.
TX: (This get bit more complicated)
Port 1: PCM
Port 2: ADC 1 & 2
Port 3: ADC 3 & 4
Port 4: DMIC-0, DMIC-1, DIMC-2
Port allocations are something like this:
RX: (Simple)
Port 1 -> HPH L/R
Port 2 -> CLASS H Amp
Port 3 -> COMP
Port 4 -> DSD.
TX: (This get bit more complicated)
Port 1: PCM
Port 2: ADC 1 & 2
Port 3: ADC 3 & 4
Port 4: DMIC-0, DMIC-1, DIMC-2 , DMIC-3 and MBHC
Port 5: DMIC-4, DMIC-5, DMIC-6 and
Thanks Pierre for your inputs,
On 20/01/2021 22:15, Pierre-Louis Bossart wrote:
On 1/20/21 12:01 PM, Srinivas Kandagatla wrote:
Some of the soundwire controllers can have static functions assigned
to each port, like some ports can only do PCM or PDM. This is the
situation
with some of the Q
On 1/20/21 12:01 PM, Srinivas Kandagatla wrote:
Some of the soundwire controllers can have static functions assigned
to each port, like some ports can only do PCM or PDM. This is the situation
with some of the Qualcomm Controllers.
In such cases its not correct to assign/map any free port on
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