Joerg Roedel wrote:
On the other hand, we want to trap cr0 so the guest can't control the
cache disable bits. Also cr4.pce and cr4.mce.
Is it a problem when the guest disables caching? It disables it only in
its own context because it has its own copy of cr0.
Some Intel processors have
On Sun, Jan 27, 2008 at 11:51:06AM +0200, Avi Kivity wrote:
> Joerg Roedel wrote:
> >
> >> What happens to lazy fpu if we don't trap cr0 changes?
> >>
> >> Perhaps it's worth disabling lazy fpu with npt.
> >>
> >
> > It should be implicitly disabled with npt because accesses to cr3 are
> > not
Joerg Roedel wrote:
What happens to lazy fpu if we don't trap cr0 changes?
Perhaps it's worth disabling lazy fpu with npt.
It should be implicitly disabled with npt because accesses to cr3 are
not intercepted anymore. The svm_set_cr3 function is the only place
which disables fpu switchi
On Sun, Jan 27, 2008 at 10:52:30AM +0200, Avi Kivity wrote:
> Joerg Roedel wrote:
> > This patch contains the SVM architecture dependent changes for KVM to enable
> > support for the Nested Paging feature of AMD Barcelona and Phenom
> > processors.
> >
> > +#ifdef CONFIG_X86_64
> > +static bool
Joerg Roedel wrote:
This patch contains the SVM architecture dependent changes for KVM to enable
support for the Nested Paging feature of AMD Barcelona and Phenom processors.
+#ifdef CONFIG_X86_64
+static bool npt_enabled = true;
+#else
static bool npt_enabled = false;
+#endif
I think th
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