> -Original Message-
> From: [EMAIL PROTECTED]
> [mailto:[EMAIL PROTECTED]]On Behalf Of
> Diefenbaugh, Paul S
>
> Chris/All:
>
> I think your assumptions are correct. I'm guessing that IDE DMA
> activity is
> not being properly handled when the CPU is in C3, resulting in memory (and
> the
?
Thanks,
-- Paul Diefenbaugh
Intel Corporation
-Original Message-
From: Christopher B. Liebman [mailto:[EMAIL PROTECTED]]
Sent: Monday, May 28, 2001 1:13 PM
To: Jens Axboe; Mark Hahn
Cc: Acpi@Phobos. Fachschaften. Tu-Muenchen. De;
[EMAIL PROTECTED]; [EMAIL PROTECTED];
[EMAIL PROTE
On Tue, 29 May 2001, Jens Axboe wrote:
> This is bull shit. If IDE didn't muck around with the request so much in
> the first place, the info could always be trusted. Even so, we have the
> hard_* numbers to go by. So this argument does not hold.
Maybe if you looked at the new code model as a wh
On Tue, May 29, 2001 at 12:56:37AM +0200, Meelis Roos wrote:
> LM> For what it is worth, in the recent postings I made about this topic, you
> LM> suggested that it was bad cabling, I swapped the cabling, same problem.
> LM> I swapped the mother board from Abit K7T to ASUS A7V and all cables worke
LM> For what it is worth, in the recent postings I made about this topic, you
LM> suggested that it was bad cabling, I swapped the cabling, same problem.
LM> I swapped the mother board from Abit K7T to ASUS A7V and all cables worked
LM> fine.
Similar info about KT7 - changing cables (both 30 and
- Original Message -
From: "Alan Cox" <[EMAIL PROTECTED]>
To: "Mark Hahn" <[EMAIL PROTECTED]>
Cc: "Jens Axboe" <[EMAIL PROTECTED]>; <[EMAIL PROTECTED]>;
<[EMAIL PROTECTED]>; <[EMAIL PROTECTED]>
Sent: Monday, May 2
On Mon, May 28 2001, Mark Hahn wrote:
> > request, when we hit a dma timout. In this case, what we really want to
> > do is retry the request in pio mode and revert to normal dma operations
> > later again.
>
> really? do we know the nature of the DMA engine problem well enough?
> is there a rea
7 matches
Mail list logo
