Dan Gora wrote:
On Feb 15, 2008 10:00 PM, Robert Hancock <[EMAIL PROTECTED]> wrote:
Well, in order for the CPU to batch up more writes you'd have to map the
BAR as either write-combining or write-back. If it's not listed in
/proc/mtrr it will be the default setting of uncacheable.
Ok, this i
On Feb 15, 2008 10:00 PM, Robert Hancock <[EMAIL PROTECTED]> wrote:
>
> Well, in order for the CPU to batch up more writes you'd have to map the
> BAR as either write-combining or write-back. If it's not listed in
> /proc/mtrr it will be the default setting of uncacheable.
Ok, this is pretty muc
Dan Gora wrote:
Hi,
I am trying to optimize a driver for a slave only PCI device and am
having a lot of trouble getting any kind of PCI burst transactions in
either the read or the write direction. Using bcopy/memcpy or even a
hand-crafted while (len) { *pdst++ = *psrc++} (with pdst and psrc
un
On Fri, 15 Feb 2008 10:00:28 -0800
"Dan Gora" <[EMAIL PROTECTED]> wrote:
> On Fri, Feb 15, 2008 at 5:02 AM, Alan Cox <[EMAIL PROTECTED]> wrote:
> > > Is there any way to get PIO to burst over the PCI bus in the read and
> > > write direction? My device has 4 BAR registers, but the area where I
>
Dan Gora wrote:
Put a DMA controller on it ;)
Ugh.. sadly that's what's coming. I really don't get why the
northbridge cannot burst however.
Because the early Intel northbridges didn't, so noone else bothered
either, since everyone designed their hardware to not require that
capability.
On Fri, Feb 15, 2008 at 5:02 AM, Alan Cox <[EMAIL PROTECTED]> wrote:
> > Is there any way to get PIO to burst over the PCI bus in the read and
> > write direction? My device has 4 BAR registers, but the area where I
>
> I think you are doign about as well as the X folks did when they spent
> ti
On Fri, Feb 15, 2008 at 2:54 AM, Andi Kleen <[EMAIL PROTECTED]> wrote:
> "Dan Gora" <[EMAIL PROTECTED]> writes:
> >
> > Is there any way to get PIO
>
> I assume you really mean MMIO, not PIO. PIO would be port IO.
Sorry, I always saw it referred to as "Programmed I/O" as opposed to DMA...
> Y
> Is there any way to get PIO to burst over the PCI bus in the read and
> write direction? My device has 4 BAR registers, but the area where I
I think you are doign about as well as the X folks did when they spent
time on trying to optimise pio transfers to and from graphics card RAM.
> Any idea
"Dan Gora" <[EMAIL PROTECTED]> writes:
>
> Is there any way to get PIO
I assume you really mean MMIO, not PIO. PIO would be port IO.
> to burst over the PCI bus in the read and
> write direction?
You should set the MMIO mapping to write combining using an MTRR
You might need to add appropiate
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