On Fri, 1 Dec 2017, Daniel Lustig wrote:
> On 12/1/2017 7:32 AM, Alan Stern wrote:
> > On Fri, 1 Dec 2017, Boqun Feng wrote:
> >>> But even on a non-other-multicopy-atomic system, there has to be some
> >>> synchronization between the memory controller and P1's CPU. Otherwise,
> >>> how could t
On Fri, Dec 01, 2017 at 08:17:04AM -0800, Daniel Lustig wrote:
> On 12/1/2017 7:32 AM, Alan Stern wrote:
> > On Fri, 1 Dec 2017, Boqun Feng wrote:
> >>> But even on a non-other-multicopy-atomic system, there has to be some
> >>> synchronization between the memory controller and P1's CPU. Otherwis
On 12/1/2017 7:32 AM, Alan Stern wrote:
> On Fri, 1 Dec 2017, Boqun Feng wrote:
>>> But even on a non-other-multicopy-atomic system, there has to be some
>>> synchronization between the memory controller and P1's CPU. Otherwise,
>>> how could the system guarantee that P1's smp_load_acquire would
On Fri, 1 Dec 2017, Boqun Feng wrote:
> > > But in case of AMOs, which directly send the addition request to memory
> > > controller, so there wouldn't be any read part or even write part of the
> > > atomic_inc() executed by CPU. Would this be allowed then?
> >
> > Firstly, sending the addition
On Thu, Nov 30, 2017 at 10:46:22AM -0500, Alan Stern wrote:
> On Thu, 30 Nov 2017, Boqun Feng wrote:
>
> > On Wed, Nov 29, 2017 at 02:44:37PM -0500, Alan Stern wrote:
> > > On Wed, 29 Nov 2017, Daniel Lustig wrote:
> > >
> > > > While we're here, let me ask about another test which isn't directly
On Thu, 30 Nov 2017, Paul E. McKenney wrote:
> > > Will, are there plans to bring this sort of thing before the standards
> > > committee?
> >
> > We discussed it, but rejected it mainly because of concerns that there could
> > be RmW operations that don't necessarily have an order-inducing depen
On Thu, Nov 30, 2017 at 08:54:35AM -0800, Paul E. McKenney wrote:
> On Thu, Nov 30, 2017 at 04:41:05PM +, Will Deacon wrote:
> > On Thu, Nov 30, 2017 at 08:14:01AM -0800, Paul E. McKenney wrote:
> > > On Thu, Nov 30, 2017 at 10:20:02AM -0500, Alan Stern wrote:
> > > > On Wed, 29 Nov 2017, Danie
On Thu, Nov 30, 2017 at 04:41:05PM +, Will Deacon wrote:
> On Thu, Nov 30, 2017 at 08:14:01AM -0800, Paul E. McKenney wrote:
> > On Thu, Nov 30, 2017 at 10:20:02AM -0500, Alan Stern wrote:
> > > On Wed, 29 Nov 2017, Daniel Lustig wrote:
> > >
> > > > On 11/29/2017 12:42 PM, Paul E. McKenney wr
On Thu, Nov 30, 2017 at 08:14:01AM -0800, Paul E. McKenney wrote:
> On Thu, Nov 30, 2017 at 10:20:02AM -0500, Alan Stern wrote:
> > On Wed, 29 Nov 2017, Daniel Lustig wrote:
> >
> > > On 11/29/2017 12:42 PM, Paul E. McKenney wrote:
> > > > On Wed, Nov 29, 2017 at 02:53:06PM -0500, Alan Stern wrote
On Thu, Nov 30, 2017 at 05:25:01PM +0100, Peter Zijlstra wrote:
> On Thu, Nov 30, 2017 at 08:14:01AM -0800, Paul E. McKenney wrote:
> > > (Also, technically speaking, the litmus test doesn't have any release
> > > operations, so no release sequence...)
> >
> > True! But if you translated it into
On Thu, Nov 30, 2017 at 08:14:01AM -0800, Paul E. McKenney wrote:
> > (Also, technically speaking, the litmus test doesn't have any release
> > operations, so no release sequence...)
>
> True! But if you translated it into C11, you would probably turn the
> smp_wmb() followed by write into a sto
On Thu, Nov 30, 2017 at 10:20:02AM -0500, Alan Stern wrote:
> On Wed, 29 Nov 2017, Daniel Lustig wrote:
>
> > On 11/29/2017 12:42 PM, Paul E. McKenney wrote:
> > > On Wed, Nov 29, 2017 at 02:53:06PM -0500, Alan Stern wrote:
> > >> On Wed, 29 Nov 2017, Peter Zijlstra wrote:
> > >>
> > >>> On Wed, N
On Thu, 30 Nov 2017, Boqun Feng wrote:
> On Wed, Nov 29, 2017 at 02:44:37PM -0500, Alan Stern wrote:
> > On Wed, 29 Nov 2017, Daniel Lustig wrote:
> >
> > > While we're here, let me ask about another test which isn't directly
> > > about unlock/lock but which is still somewhat related to this
> >
On Wed, 29 Nov 2017, Daniel Lustig wrote:
> On 11/29/2017 12:42 PM, Paul E. McKenney wrote:
> > On Wed, Nov 29, 2017 at 02:53:06PM -0500, Alan Stern wrote:
> >> On Wed, 29 Nov 2017, Peter Zijlstra wrote:
> >>
> >>> On Wed, Nov 29, 2017 at 11:04:53AM -0800, Daniel Lustig wrote:
> >>>
> While w
On Wed, Nov 29, 2017 at 08:46:02PM +0100, Peter Zijlstra wrote:
> On Wed, Nov 29, 2017 at 11:04:53AM -0800, Daniel Lustig wrote:
>
> > While we're here, let me ask about another test which isn't directly
> > about unlock/lock but which is still somewhat related to this
> > discussion:
> >
> > "MP
On Thu, Nov 30, 2017 at 04:55:09PM +0800, Boqun Feng wrote:
> But in case of AMOs, which directly send the addition request to memory
> controller, so there wouldn't be any read part or even write part of the
> atomic_inc() executed by CPU. Would this be allowed then?
Personally I bloody hate AMOs
On Wed, Nov 29, 2017 at 02:44:37PM -0500, Alan Stern wrote:
> On Wed, 29 Nov 2017, Daniel Lustig wrote:
>
> > While we're here, let me ask about another test which isn't directly
> > about unlock/lock but which is still somewhat related to this
> > discussion:
> >
> > "MP+wmb+xchg-acq" (or some s
On Wed, Nov 29, 2017 at 02:18:48PM -0800, Daniel Lustig wrote:
> On 11/29/2017 12:42 PM, Paul E. McKenney wrote:
> > On Wed, Nov 29, 2017 at 02:53:06PM -0500, Alan Stern wrote:
> >> On Wed, 29 Nov 2017, Peter Zijlstra wrote:
> >>
> >>> On Wed, Nov 29, 2017 at 11:04:53AM -0800, Daniel Lustig wrote:
On 11/29/2017 12:42 PM, Paul E. McKenney wrote:
> On Wed, Nov 29, 2017 at 02:53:06PM -0500, Alan Stern wrote:
>> On Wed, 29 Nov 2017, Peter Zijlstra wrote:
>>
>>> On Wed, Nov 29, 2017 at 11:04:53AM -0800, Daniel Lustig wrote:
>>>
While we're here, let me ask about another test which isn't dire
On Wed, Nov 29, 2017 at 02:53:06PM -0500, Alan Stern wrote:
> On Wed, 29 Nov 2017, Peter Zijlstra wrote:
>
> > On Wed, Nov 29, 2017 at 11:04:53AM -0800, Daniel Lustig wrote:
> >
> > > While we're here, let me ask about another test which isn't directly
> > > about unlock/lock but which is still s
On Wed, Nov 29, 2017 at 11:04:53AM -0800, Daniel Lustig wrote:
> "MP+wmb+xchg-acq" (or some such)
>
> {}
>
> P0(int *x, int *y)
> {
> WRITE_ONCE(*x, 1);
> smp_wmb();
> WRITE_ONCE(*y, 1);
> }
>
> P1(int *x, int *y)
> {
> r1 = atomic_xchg_relaxed(y, 2);
> r2
On Wed, 29 Nov 2017, Peter Zijlstra wrote:
> On Wed, Nov 29, 2017 at 11:04:53AM -0800, Daniel Lustig wrote:
>
> > While we're here, let me ask about another test which isn't directly
> > about unlock/lock but which is still somewhat related to this
> > discussion:
> >
> > "MP+wmb+xchg-acq" (or s
On Wed, Nov 29, 2017 at 11:04:53AM -0800, Daniel Lustig wrote:
> While we're here, let me ask about another test which isn't directly
> about unlock/lock but which is still somewhat related to this
> discussion:
>
> "MP+wmb+xchg-acq" (or some such)
>
> {}
>
> P0(int *x, int *y)
> {
> WR
On Wed, 29 Nov 2017, Daniel Lustig wrote:
> While we're here, let me ask about another test which isn't directly
> about unlock/lock but which is still somewhat related to this
> discussion:
>
> "MP+wmb+xchg-acq" (or some such)
>
> {}
>
> P0(int *x, int *y)
> {
> WRITE_ONCE(*x, 1);
>
On Wed, Nov 29, 2017 at 11:04:53AM -0800, Daniel Lustig wrote:
> On 11/27/2017 1:16 PM, Alan Stern wrote:
> > This is essentially a repeat of an email I sent out before the
> > Thanksgiving holiday, the assumption being that lack of any responses
> > was caused by the holiday break. (And this time
On 11/27/2017 1:16 PM, Alan Stern wrote:
> This is essentially a repeat of an email I sent out before the
> Thanksgiving holiday, the assumption being that lack of any responses
> was caused by the holiday break. (And this time the message is CC'ed
> to LKML, so there will be a public record of it
On Mon, Nov 27, 2017 at 04:16:47PM -0500, Alan Stern wrote:
> This is essentially a repeat of an email I sent out before the
> Thanksgiving holiday, the assumption being that lack of any responses
> was caused by the holiday break. (And this time the message is CC'ed
> to LKML, so there will be a
On Mon, Nov 27, 2017 at 03:28:03PM -0800, Daniel Lustig wrote:
> On 11/27/2017 1:16 PM, Alan Stern wrote:> C rel-acq-write-ordering-3
> >
> > {}
> >
> > P0(int *x, int *s, int *y)
> > {
> > WRITE_ONCE(*x, 1);
> > smp_store_release(s, 1);
> > r1 = smp_load_acquire(s);
> > WRITE_ONC
On 11/27/2017 1:16 PM, Alan Stern wrote:> C rel-acq-write-ordering-3
>
> {}
>
> P0(int *x, int *s, int *y)
> {
> WRITE_ONCE(*x, 1);
> smp_store_release(s, 1);
> r1 = smp_load_acquire(s);
> WRITE_ONCE(*y, 1);
> }
>
> P1(int *x, int *y)
> {
> r2 = READ_ONCE(*y);
>
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