Re: common clock framwork: clk_set_rate issue

2012-12-19 Thread Sascha Hauer
On Wed, Dec 19, 2012 at 02:49:25PM +0800, Chao Xie wrote: > On Tue, Dec 18, 2012 at 3:47 PM, Sascha Hauer wrote: > >> There is already a flag to do it. > >> CLK_SET_RATE_PARENT > > > > That flag has another meaning. It means that a clock is allowed to > > change the parents rate when a rate change

Re: common clock framwork: clk_set_rate issue

2012-12-18 Thread Chao Xie
On Tue, Dec 18, 2012 at 3:47 PM, Sascha Hauer wrote: > On Tue, Dec 18, 2012 at 10:19:21AM +0800, Chao Xie wrote: >> On Tue, Dec 18, 2012 at 4:19 AM, Sascha Hauer wrote: >> > On Thu, Dec 06, 2012 at 10:52:03AM +0800, Chao Xie wrote: >> >> hi >> >> When develop the clk drivers for SOCs based on com

Re: common clock framwork: clk_set_rate issue

2012-12-17 Thread Sascha Hauer
On Tue, Dec 18, 2012 at 10:19:21AM +0800, Chao Xie wrote: > On Tue, Dec 18, 2012 at 4:19 AM, Sascha Hauer wrote: > > On Thu, Dec 06, 2012 at 10:52:03AM +0800, Chao Xie wrote: > >> hi > >> When develop the clk drivers for SOCs based on common clock framework. > >> I met a issue. > >> For example th

Re: common clock framwork: clk_set_rate issue

2012-12-17 Thread Chao Xie
On Tue, Dec 18, 2012 at 4:19 AM, Sascha Hauer wrote: > On Thu, Dec 06, 2012 at 10:52:03AM +0800, Chao Xie wrote: >> hi >> When develop the clk drivers for SOCs based on common clock framework. >> I met a issue. >> For example there is a uart device, it's function clock comes from a >> divider, and

Re: common clock framwork: clk_set_rate issue

2012-12-17 Thread Sascha Hauer
On Thu, Dec 06, 2012 at 10:52:03AM +0800, Chao Xie wrote: > hi > When develop the clk drivers for SOCs based on common clock framework. > I met a issue. > For example there is a uart device, it's function clock comes from a > divider, and the divider's parent is a mux. It means > > MUX --> DIV -->