Re: Relax CPU features sanity checking on heterogeneous architectures

2019-10-18 Thread Marc Zyngier
On Fri, 18 Oct 2019 15:33:29 +0100, Stephen Boyd wrote: > > Quoting Marc Zyngier (2019-10-18 00:20:56) > > > > If this SoC is anythinig like SM8150, 32bit guests will be hit and > > miss, > > depending on the CPU your guest runs on, or is migrated to. We need to > > either drop capabilities

Re: Relax CPU features sanity checking on heterogeneous architectures

2019-10-18 Thread Stephen Boyd
Quoting Marc Zyngier (2019-10-18 00:20:56) > > If this SoC is anythinig like SM8150, 32bit guests will be hit and > miss, > depending on the CPU your guest runs on, or is migrated to. We need to > either drop capabilities from the 32bit-capable CPU, or prevent the > non-32bit capable CPU from

Re: Relax CPU features sanity checking on heterogeneous architectures

2019-10-18 Thread Sai Prakash Ranjan
On 2019-10-18 01:30, Stephen Boyd wrote: Quoting Sai Prakash Ranjan (2019-10-11 06:40:13) On 2019-10-11 19:04, Marc Zyngier wrote: > On Fri, 11 Oct 2019 18:47:39 +0530 > Sai Prakash Ranjan wrote: > >> Hi Mark, >> >> Thanks a lot for the detailed explanations, I did have a look at all >> the

Re: Relax CPU features sanity checking on heterogeneous architectures

2019-10-18 Thread Catalin Marinas
On Thu, Oct 17, 2019 at 04:39:23PM -0500, Jeremy Linton wrote: > On 10/11/19 8:54 AM, Mark Rutland wrote: > > On Fri, Oct 11, 2019 at 02:33:43PM +0100, Marc Zyngier wrote: > > > On Fri, 11 Oct 2019 11:50:11 +0100 > > > Mark Rutland wrote: > > > > On Fri, Oct 11, 2019 at 11:19:00AM +0530, Sai

Re: Relax CPU features sanity checking on heterogeneous architectures

2019-10-18 Thread Marc Zyngier
On 2019-10-17 21:00, Stephen Boyd wrote: Quoting Sai Prakash Ranjan (2019-10-11 06:40:13) On 2019-10-11 19:04, Marc Zyngier wrote: > On Fri, 11 Oct 2019 18:47:39 +0530 > Sai Prakash Ranjan wrote: > >> Hi Mark, >> >> Thanks a lot for the detailed explanations, I did have a look at all >> the

Re: Relax CPU features sanity checking on heterogeneous architectures

2019-10-17 Thread Jeremy Linton
Hi, On 10/11/19 8:54 AM, Mark Rutland wrote: On Fri, Oct 11, 2019 at 02:33:43PM +0100, Marc Zyngier wrote: On Fri, 11 Oct 2019 11:50:11 +0100 Mark Rutland wrote: Hi, On Fri, Oct 11, 2019 at 11:19:00AM +0530, Sai Prakash Ranjan wrote: On latest QCOM SoCs like SM8150 and SC7180 with

Re: Relax CPU features sanity checking on heterogeneous architectures

2019-10-17 Thread Stephen Boyd
Quoting Sai Prakash Ranjan (2019-10-11 06:40:13) > On 2019-10-11 19:04, Marc Zyngier wrote: > > On Fri, 11 Oct 2019 18:47:39 +0530 > > Sai Prakash Ranjan wrote: > > > >> Hi Mark, > >> > >> Thanks a lot for the detailed explanations, I did have a look at all > >> the variations before posting

Re: Relax CPU features sanity checking on heterogeneous architectures

2019-10-11 Thread Marc Zyngier
On Fri, 11 Oct 2019 14:54:31 +0100 Mark Rutland wrote: > On Fri, Oct 11, 2019 at 02:33:43PM +0100, Marc Zyngier wrote: > > On Fri, 11 Oct 2019 11:50:11 +0100 > > Mark Rutland wrote: > > > > > Hi, > > > > > > On Fri, Oct 11, 2019 at 11:19:00AM +0530, Sai Prakash Ranjan wrote: > > > > On

Re: Relax CPU features sanity checking on heterogeneous architectures

2019-10-11 Thread Mark Rutland
On Fri, Oct 11, 2019 at 02:33:43PM +0100, Marc Zyngier wrote: > On Fri, 11 Oct 2019 11:50:11 +0100 > Mark Rutland wrote: > > > Hi, > > > > On Fri, Oct 11, 2019 at 11:19:00AM +0530, Sai Prakash Ranjan wrote: > > > On latest QCOM SoCs like SM8150 and SC7180 with big.LITTLE arch, below > > >

Re: Relax CPU features sanity checking on heterogeneous architectures

2019-10-11 Thread Sai Prakash Ranjan
On 2019-10-11 19:04, Marc Zyngier wrote: On Fri, 11 Oct 2019 18:47:39 +0530 Sai Prakash Ranjan wrote: Hi Mark, Thanks a lot for the detailed explanations, I did have a look at all the variations before posting this. On 2019-10-11 16:20, Mark Rutland wrote: > Hi, > > On Fri, Oct 11, 2019

Re: Relax CPU features sanity checking on heterogeneous architectures

2019-10-11 Thread Marc Zyngier
On Fri, 11 Oct 2019 18:47:39 +0530 Sai Prakash Ranjan wrote: > Hi Mark, > > Thanks a lot for the detailed explanations, I did have a look at all the > variations before posting this. > > On 2019-10-11 16:20, Mark Rutland wrote: > > Hi, > > > > On Fri, Oct 11, 2019 at 11:19:00AM +0530, Sai

Re: Relax CPU features sanity checking on heterogeneous architectures

2019-10-11 Thread Marc Zyngier
On Fri, 11 Oct 2019 11:50:11 +0100 Mark Rutland wrote: > Hi, > > On Fri, Oct 11, 2019 at 11:19:00AM +0530, Sai Prakash Ranjan wrote: > > On latest QCOM SoCs like SM8150 and SC7180 with big.LITTLE arch, below > > warnings are observed during bootup of big cpu cores. > > For reference, which

Re: Relax CPU features sanity checking on heterogeneous architectures

2019-10-11 Thread Sai Prakash Ranjan
Hi Mark, Thanks a lot for the detailed explanations, I did have a look at all the variations before posting this. On 2019-10-11 16:20, Mark Rutland wrote: Hi, On Fri, Oct 11, 2019 at 11:19:00AM +0530, Sai Prakash Ranjan wrote: On latest QCOM SoCs like SM8150 and SC7180 with big.LITTLE

Re: Relax CPU features sanity checking on heterogeneous architectures

2019-10-11 Thread Mark Rutland
Hi, On Fri, Oct 11, 2019 at 11:19:00AM +0530, Sai Prakash Ranjan wrote: > On latest QCOM SoCs like SM8150 and SC7180 with big.LITTLE arch, below > warnings are observed during bootup of big cpu cores. For reference, which CPUs are in those SoCs? > SM8150: > > [0.271177] CPU features:

Relax CPU features sanity checking on heterogeneous architectures

2019-10-10 Thread Sai Prakash Ranjan
On latest QCOM SoCs like SM8150 and SC7180 with big.LITTLE arch, below warnings are observed during bootup of big cpu cores. SM8150: [0.271177] CPU features: SANITY CHECK: Unexpected variation in SYS_ID_AA64PFR0_EL1. Boot CPU: 0x00, CPU4: 0x001112 [0.271184] CPU