On Fri, Jun 12, 2015 at 03:12:13PM +0530, Sreekanth Reddy wrote:
> In this patch, increased the number of MSIX vector support for SAS3 C0 HBAs
> to up-to 96.
>
> Following are changes that are done in this patch
> 1. Support this feature only for SAS3 C0 cards and also only
In this patch, increased the number of MSIX vector support for SAS3 C0 HBAs to
up-to 96.
Following are changes that are done in this patch
1. Support this feature only for SAS3 C0 cards and also only when reply post
free queue count is greater than 8.
2. Instead of using single
In this patch, increased the number of MSIX vector support for SAS3 C0 HBAs to
up-to 96.
Following are changes that are done in this patch
1. Support this feature only for SAS3 C0 cards and also only when reply post
free queue count is greater than 8.
2. Instead of using single
On Fri, Jun 12, 2015 at 03:12:13PM +0530, Sreekanth Reddy wrote:
In this patch, increased the number of MSIX vector support for SAS3 C0 HBAs
to up-to 96.
Following are changes that are done in this patch
1. Support this feature only for SAS3 C0 cards and also only when reply post
free
, increased the number of MSIX vector support for SAS3 C0 HBAs
to up-to 96.
Following are changes that are done in this patch
1. Support this feature only for SAS3 C0 cards and also only when reply post
free queue count is greater than 8.
2. Instead of using single ReplyPostHostIndex system
will only claim the funds if we don’t act
now and receive the funds.
This is a mutual deal that we both stand to benefit so much from.
All I need is your utmost trust, confidence and sincerity.
You also have to guarantee me that I will receive my share after the transfer.
Do reply urgently so
will only claim the funds if we don’t act
now and receive the funds.
This is a mutual deal that we both stand to benefit so much from.
All I need is your utmost trust, confidence and sincerity.
You also have to guarantee me that I will receive my share after the transfer.
Do reply urgently so
Dear Friend,
i need your kind attention. I will be very glad if you do assist me to relocate
this sumof( $15.Million US dollars.) to your bank account for the benefit of our
both families.
only i cannot operate it alone without using a Foreigner who will stand as a
beneficiary to the money,
Dear Friend,
i need your kind attention. I will be very glad if you do assist me to relocate
this sumof( $15.Million US dollars.) to your bank account for the benefit of our
both families.
only i cannot operate it alone without using a Foreigner who will stand as a
beneficiary to the money,
)
- req = xprt_lookup_rqst(bc_xprt, xid);
-
- if (!req) {
- printk(KERN_NOTICE
- "%s: Got unrecognized reply: "
- "calldir 0x%x xpt_bc_xprt %p xid %08x\n",
- __f
receive_cb_reply(struct svc_sock *svsk,
struct svc_rqst *rqstp)
xid = *p++;
calldir = *p;
- if (bc_xprt)
- req = xprt_lookup_rqst(bc_xprt, xid);
-
- if (!req) {
- printk(KERN_NOTICE
- %s: Got unrecognized reply
as a foreigner because this money can not be approved to a local
person here.
Reply urgently so that I will inform you the next step to take urgently.
Sincerely,
Richard Williams.
Reply to this e-mail addess:rw72...@gmail.com
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as a foreigner because this money can not be approved to a local
person here.
Reply urgently so that I will inform you the next step to take urgently.
Sincerely,
Richard Williams.
Reply to this e-mail addess:rw72...@gmail.com
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On Thu, 2015-04-02 at 16:39 +1100, Benjamin Herrenschmidt wrote:
> On Thu, 2015-02-19 at 21:45 -0800, James Bottomley wrote:
>
> > Ben, this is legal by design. It was specifically designed for the
> > aic79xx SCSI card, but can be used for a variety of other reasons. The
> > aic79xx hardware
On Thu, 2015-04-02 at 16:39 +1100, Benjamin Herrenschmidt wrote:
On Thu, 2015-02-19 at 21:45 -0800, James Bottomley wrote:
Ben, this is legal by design. It was specifically designed for the
aic79xx SCSI card, but can be used for a variety of other reasons. The
aic79xx hardware problem
On Thu, 2015-02-19 at 21:45 -0800, James Bottomley wrote:
> Ben, this is legal by design. It was specifically designed for the
> aic79xx SCSI card, but can be used for a variety of other reasons. The
> aic79xx hardware problem was that the DMA engine could address the whole
> of memory (it had
to a local
person here.
Reply urgently so that I will inform you the next step to take urgently.
Sincerely,
Richard Williams.
Reply to this e-mail addess:richard_william...@outlook.com
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On Thu, 2015-02-19 at 21:45 -0800, James Bottomley wrote:
Ben, this is legal by design. It was specifically designed for the
aic79xx SCSI card, but can be used for a variety of other reasons. The
aic79xx hardware problem was that the DMA engine could address the whole
of memory (it had two
to a local
person here.
Reply urgently so that I will inform you the next step to take urgently.
Sincerely,
Richard Williams.
Reply to this e-mail addess:richard_william...@outlook.com
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In this patch, increased the number of MSIX vector support for SAS3 C0 HBAs to
up-to 96.
Following are changes that are done in this patch
1. Support this feature only for SAS3 C0 cards and also only when reply post
free queue count is greater than 8.
2. Instead of using single
In this patch, increased the number of MSIX vector support for SAS3 C0 HBAs to
up-to 96.
Following are changes that are done in this patch
1. Support this feature only for SAS3 C0 cards and also only when reply post
free queue count is greater than 8.
2. Instead of using single
I have business finance proposition for you. Reply for details
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Please read the FA
I have business finance proposition for you. Reply for details
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Please read the FAQ at http
--
How are you doing? It's a wonderful compliment to write to you today.
My name is Carolina. I am a Simple and Honest girl. I have something
to tell you, perhaps you might be of assistance to me. I Had always
wanted to be a medical Doctor and my teachers in school used to
encourage me that I
On Thu, 2015-02-19 at 21:45 -0800, James Bottomley wrote:
> Ben, this is legal by design. It was specifically designed for the
> aic79xx SCSI card, but can be used for a variety of other reasons. The
> aic79xx hardware problem was that the DMA engine could address the whole
> of memory (it had
On Fri, 2015-02-20 at 16:22 +1100, Benjamin Herrenschmidt wrote:
> Looking a bit more closely, you basically do
>
> - set_dma_mask(64-bit)
> - set_consistent_dma_mask(32-bit)
>
> Now, I don't know how x86 will react to the conflicting masks, but on
> ppc64, I'm pretty sure the second one will
On Fri, 2015-02-20 at 16:22 +1100, Benjamin Herrenschmidt wrote:
> On Fri, 2015-02-20 at 16:06 +1100, Benjamin Herrenschmidt wrote:
>
> > Note that even on powerpc platforms where it would work because we
> > maintain both 32-bit and 64-bit bypass windows in the device address
> > space
On Fri, 2015-02-20 at 16:06 +1100, Benjamin Herrenschmidt wrote:
> Note that even on powerpc platforms where it would work because we
> maintain both 32-bit and 64-bit bypass windows in the device address
> space simultaneously, you will leak iommu entries unless you also switch
> back to 32-bit
On Fri, 2015-02-20 at 16:01 +1100, Benjamin Herrenschmidt wrote:
> Hi Sreekanth !
>
> While looking at some (unrelated) issue where mtp2sas seems to be using
> 32-bit DMA instead of 64-bit DMA on some POWER platforms, I noticed this
> patch which was merged as
Hi Sreekanth !
While looking at some (unrelated) issue where mtp2sas seems to be using
32-bit DMA instead of 64-bit DMA on some POWER platforms, I noticed this
patch which was merged as 5fb1bf8aaa832e1e9ca3198de7bbecb8eff7db9c.
Can you confirm my understanding that you are:
- Setting the DMA
was inclusive, secondly, in the same file
of yours, there is a letter here stating that you are dead, so based on this,
we are contacting you to verify the true position of your status, and you have
only 48hours to reply this mail or we will work with what we saw in your file
that you are dead, and I
was inclusive, secondly, in the same file
of yours, there is a letter here stating that you are dead, so based on this,
we are contacting you to verify the true position of your status, and you have
only 48hours to reply this mail or we will work with what we saw in your file
that you are dead, and I
On Fri, 2015-02-20 at 16:01 +1100, Benjamin Herrenschmidt wrote:
Hi Sreekanth !
While looking at some (unrelated) issue where mtp2sas seems to be using
32-bit DMA instead of 64-bit DMA on some POWER platforms, I noticed this
patch which was merged as 5fb1bf8aaa832e1e9ca3198de7bbecb8eff7db9c.
--
How are you doing? It's a wonderful compliment to write to you today.
My name is Carolina. I am a Simple and Honest girl. I have something
to tell you, perhaps you might be of assistance to me. I Had always
wanted to be a medical Doctor and my teachers in school used to
encourage me that I
On Fri, 2015-02-20 at 16:22 +1100, Benjamin Herrenschmidt wrote:
Looking a bit more closely, you basically do
- set_dma_mask(64-bit)
- set_consistent_dma_mask(32-bit)
Now, I don't know how x86 will react to the conflicting masks, but on
ppc64, I'm pretty sure the second one will barf.
On Thu, 2015-02-19 at 21:45 -0800, James Bottomley wrote:
Ben, this is legal by design. It was specifically designed for the
aic79xx SCSI card, but can be used for a variety of other reasons. The
aic79xx hardware problem was that the DMA engine could address the whole
of memory (it had two
Hi Sreekanth !
While looking at some (unrelated) issue where mtp2sas seems to be using
32-bit DMA instead of 64-bit DMA on some POWER platforms, I noticed this
patch which was merged as 5fb1bf8aaa832e1e9ca3198de7bbecb8eff7db9c.
Can you confirm my understanding that you are:
- Setting the DMA
On Fri, 2015-02-20 at 16:06 +1100, Benjamin Herrenschmidt wrote:
Note that even on powerpc platforms where it would work because we
maintain both 32-bit and 64-bit bypass windows in the device address
space simultaneously, you will leak iommu entries unless you also switch
back to 32-bit when
On Fri, 2015-02-20 at 16:22 +1100, Benjamin Herrenschmidt wrote:
On Fri, 2015-02-20 at 16:06 +1100, Benjamin Herrenschmidt wrote:
Note that even on powerpc platforms where it would work because we
maintain both 32-bit and 64-bit bypass windows in the device address
space simultaneously,
From: Sage Weil
3.4.105-rc1 review patch. If anyone has any objections, please let me know.
--
commit 73c3d4812b4c755efeca0140f606f83772a39ce4 upstream.
We preallocate a few of the message types we get back from the mon. If we
get a larger message than we are expecting,
From: Sage Weil s...@redhat.com
3.4.105-rc1 review patch. If anyone has any objections, please let me know.
--
commit 73c3d4812b4c755efeca0140f606f83772a39ce4 upstream.
We preallocate a few of the message types we get back from the mon. If we
get a larger message than we are
;
- if (bc_xprt)
- req = xprt_lookup_rqst(bc_xprt, xid);
-
- if (!req) {
- printk(KERN_NOTICE
- "%s: Got unrecognized reply: "
- "calldir 0x%x xpt_bc_xprt %p xid %08x\n",
- __f
;
- if (bc_xprt)
- req = xprt_lookup_rqst(bc_xprt, xid);
-
- if (!req) {
- printk(KERN_NOTICE
- "%s: Got unrecognized reply: "
- "calldir 0x%x xpt_bc_xprt %p xid %08x\n",
-
unrecognized reply:
- calldir 0x%x xpt_bc_xprt %p xid %08x\n,
- __func__, ntohl(calldir),
- bc_xprt, xid);
+ if (!bc_xprt)
return -EAGAIN;
- }
+ spin_lock_bh(bc_xprt-transport_lock);
+ req
int receive_cb_reply(struct svc_sock *svsk, struct
svc_rqst *rqstp)
xid = *p++;
calldir = *p;
- if (bc_xprt)
- req = xprt_lookup_rqst(bc_xprt, xid);
-
- if (!req) {
- printk(KERN_NOTICE
- %s: Got unrecognized reply
- "%s: Got unrecognized reply: "
- "calldir 0x%x xpt_bc_xprt %p xid %08x\n",
- __func__, ntohl(calldir),
- bc_xprt, ntohl(xid));
+ if (!bc_xprt)
return -EAGAIN;
- }
+
)
- req = xprt_lookup_rqst(bc_xprt, xid);
-
- if (!req) {
- printk(KERN_NOTICE
- %s: Got unrecognized reply:
- calldir 0x%x xpt_bc_xprt %p xid %08x\n,
- __func__, ntohl(calldir
From: Sage Weil
3.4.105-rc1 review patch. If anyone has any objections, please let me know.
--
commit 73c3d4812b4c755efeca0140f606f83772a39ce4 upstream.
We preallocate a few of the message types we get back from the mon. If we
get a larger message than we are expecting,
From: Sage Weil s...@redhat.com
3.4.105-rc1 review patch. If anyone has any objections, please let me know.
--
commit 73c3d4812b4c755efeca0140f606f83772a39ce4 upstream.
We preallocate a few of the message types we get back from the mon. If we
get a larger message than we are
In this patch, increased the number of MSIX vector support for SAS3 C0 HBAs to
up-to 96.
Following are changes that are done in this patch
1. Support this feature only for SAS3 C0 cards and also only when reply post
free queue count is greater than 8.
2. Instead of using single
In this patch, increased the number of MSIX vector support for SAS3 C0 HBAs to
up-to 96.
Following are changes that are done in this patch
1. Support this feature only for SAS3 C0 cards and also only when reply post
free queue count is greater than 8.
2. Instead of using single
3.2.64-rc1 review patch. If anyone has any objections, please let me know.
--
From: Sage Weil
commit 73c3d4812b4c755efeca0140f606f83772a39ce4 upstream.
We preallocate a few of the message types we get back from the mon. If we
get a larger message than we are expecting, fall
3.2.64-rc1 review patch. If anyone has any objections, please let me know.
--
From: Sage Weil s...@redhat.com
commit 73c3d4812b4c755efeca0140f606f83772a39ce4 upstream.
We preallocate a few of the message types we get back from the mon. If we
get a larger message than we are
Dear Sir/Madam, Here is a pdf attachment of my proposal to you. Please
read and reply I would be grateful. Jose Calvache
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Dear Sir/Madam, Here is a pdf attachment of my proposal to you. Please
read and reply I would be grateful. Jose Calvache
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Dear Sir/Madam, Here is a pdf attachment of my proposal to you. Please
read and reply I would be grateful. Jose Calvache
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Dear Sir/Madam, Here is a pdf attachment of my proposal to you. Please
read and reply I would be grateful. Jose Calvache
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3.13.11.9 -stable review patch. If anyone has any objections, please let me
know.
--
From: Sage Weil
commit 73c3d4812b4c755efeca0140f606f83772a39ce4 upstream.
We preallocate a few of the message types we get back from the mon. If we
get a larger message than we are
3.13.11.9 -stable review patch. If anyone has any objections, please let me
know.
--
From: Sage Weil s...@redhat.com
commit 73c3d4812b4c755efeca0140f606f83772a39ce4 upstream.
We preallocate a few of the message types we get back from the mon. If we
get a larger message than
Sequel to your non-response to my previous email, I am re-sending this to you
again thus; A deceased client of mine who died of a heart-related ailment about
3 years ago left behind some funds which I want you to assist in retriving and
distributing. Reply so I can give you details on what
Sequel to your non-response to my previous email, I am re-sending this to you
again thus; A deceased client of mine who died of a heart-related ailment about
3 years ago left behind some funds which I want you to assist in retriving and
distributing. Reply so I can give you details.
Regards
Sequel to your non-response to my previous email, I am re-sending this to you
again thus; A deceased client of mine who died of a heart-related ailment about
3 years ago left behind some funds which I want you to assist in retriving and
distributing. Reply so I can give you details on what
From: Sage Weil
3.12-stable review patch. If anyone has any objections, please let me know.
===
commit 73c3d4812b4c755efeca0140f606f83772a39ce4 upstream.
We preallocate a few of the message types we get back from the mon. If we
get a larger message than we are expecting, fall
From: Sage Weil s...@redhat.com
3.12-stable review patch. If anyone has any objections, please let me know.
===
commit 73c3d4812b4c755efeca0140f606f83772a39ce4 upstream.
We preallocate a few of the message types we get back from the mon. If we
get a larger message than we are
3.16-stable review patch. If anyone has any objections, please let me know.
--
From: Sage Weil
commit 73c3d4812b4c755efeca0140f606f83772a39ce4 upstream.
We preallocate a few of the message types we get back from the mon. If we
get a larger message than we are expecting, fall
3.14-stable review patch. If anyone has any objections, please let me know.
--
From: Sage Weil
commit 73c3d4812b4c755efeca0140f606f83772a39ce4 upstream.
We preallocate a few of the message types we get back from the mon. If we
get a larger message than we are expecting, fall
3.14-stable review patch. If anyone has any objections, please let me know.
--
From: Sage Weil s...@redhat.com
commit 73c3d4812b4c755efeca0140f606f83772a39ce4 upstream.
We preallocate a few of the message types we get back from the mon. If we
get a larger message than we are
3.16-stable review patch. If anyone has any objections, please let me know.
--
From: Sage Weil s...@redhat.com
commit 73c3d4812b4c755efeca0140f606f83772a39ce4 upstream.
We preallocate a few of the message types we get back from the mon. If we
get a larger message than we are
Dear,
I know that this letter may come to you as a surprise, I got your contact
address from the computerized search. My name is Mr Alif Tomar, I am the Bill
and Exchange (assistant) Manager of Bank of Africa Ouagadougou, Burkina Faso.
In my department I discovered an abandoned sum of
Dear,
I know that this letter may come to you as a surprise, I got your contact
address from the computerized search. My name is Mr Alif Tomar, I am the Bill
and Exchange (assistant) Manager of Bank of Africa Ouagadougou, Burkina Faso.
In my department I discovered an abandoned sum of
Up to now, Driver allocates a single contiguous block of memory
pool for all reply queues and passes down a single address in the
ReplyDescriptorPostQueueAddress field of the IOC Init Request
Message to the firmware.
When firmware receives this address, it will program each of the
Reply
Up to now, Driver allocates a single contiguous block of memory
pool for all reply queues and passes down a single address in the
ReplyDescriptorPostQueueAddress field of the IOC Init Request
Message to the firmware.
When firmware receives this address, it will program each of the
Reply
Up to now, Driver allocates a single contiguous block of memory
pool for all reply queues and passes down a single address in the
ReplyDescriptorPostQueueAddress field of the IOC Init Request
Message to the firmware.
When firmware receives this address, it will program each of the
Reply
Up to now, Driver allocates a single contiguous block of memory
pool for all reply queues and passes down a single address in the
ReplyDescriptorPostQueueAddress field of the IOC Init Request
Message to the firmware.
When firmware receives this address, it will program each of the
Reply
sum while 70% will be for me, please reply back to me urgent if you
are interested to enable me provide you more details.
Best regards,
Mr. David Z.
---
San-chung Commercial and Industrial Vocational High School
http://www.scvs.ntpc.edu.tw
æ°åå¸ç«ä¸éé«ç´åå
sum while 70% will be for me, please reply back to me urgent if you
are interested to enable me provide you more details.
Best regards,
Mr. David Z.
---
San-chung Commercial and Industrial Vocational High School
http://www.scvs.ntpc.edu.tw
æ°åå¸ç«ä¸éé«ç´åå
Can you please send me a single big series with all the mpt2 and mpt3
updates? With all the resends I'm losing track.
Please also pick up third party mpt patches like
'[PATCH 3/3] mpt3sas, mpt2sas: fix scsi_add_host error handling problems in
_scsih_probe' from Robert Elliott.
And while I
Can you please send me a single big series with all the mpt2 and mpt3
updates? With all the resends I'm losing track.
Please also pick up third party mpt patches like
'[PATCH 3/3] mpt3sas, mpt2sas: fix scsi_add_host error handling problems in
_scsih_probe' from Robert Elliott.
And while I
Up to now, Driver allocates a single contiguous block of memory
pool for all reply queues and passes down a single address in the
ReplyDescriptorPostQueueAddress field of the IOC Init Request
Message to the firmware.
When firmware receives this address, it will program each of the
Reply
, consistent_dma_mask))
Up to now, Driver allocates a single contiguous block of memory
pool for all reply queues and passes down a single address in the
ReplyDescriptorPostQueueAddress field of the IOC Init Request
Message to the firmware.
When firmware receives this address, it will program each of the
Reply
Up to now, Driver allocates a single contiguous block of memory
pool for all reply queues and passes down a single address in the
ReplyDescriptorPostQueueAddress field of the IOC Init Request
Message to the firmware.
When firmware receives this address, it will program each of the
Reply
Up to now, Driver allocates a single contiguous block of memory
pool for all reply queues and passes down a single address in the
ReplyDescriptorPostQueueAddress field of the IOC Init Request
Message to the firmware.
When firmware receives this address, it will program each of the
Reply
, consistent_dma_mask))
Up to now, Driver allocates a single contiguous block of memory
pool for all reply queues and passes down a single address in the
ReplyDescriptorPostQueueAddress field of the IOC Init Request
Message to the firmware.
When firmware receives this address, it will program each of the
Reply
Up to now, Driver allocates a single contiguous block of memory
pool for all reply queues and passes down a single address in the
ReplyDescriptorPostQueueAddress field of the IOC Init Request
Message to the firmware.
When firmware receives this address, it will program each of the
Reply
>>>>> "Sreekanth" == Sreekanth Reddy writes:
Sreekanth> Sending the this patch once agin using git send-email. Up to
Sreekanth> now, Driver allocates a single contiguous block of memory
Sreekanth> pool for all reply queues and passes
Sreekanth == Sreekanth Reddy sreekanth.re...@avagotech.com writes:
Sreekanth Sending the this patch once agin using git send-email. Up to
Sreekanth now, Driver allocates a single contiguous block of memory
Sreekanth pool for all reply queues and passes down a single address in
Sreekanth
On Tue, Aug 12, 2014 at 3:07 PM, Joe Perches wrote:
> On Tue, 2014-08-12 at 14:54 +0530, Sreekanth Reddy wrote:
>> So, the proposal is to allocate memory independently for each
>> Reply Queue and pass down all of the addresses to the firmware.
>> Then the firmware will j
On Tue, 2014-08-12 at 14:54 +0530, Sreekanth Reddy wrote:
> So, the proposal is to allocate memory independently for each
> Reply Queue and pass down all of the addresses to the firmware.
> Then the firmware will just take each address and program the value
> into the correct regist
Sending this patch once again using git send-email.
Up to now, Driver allocates a single contiguous block of memory
pool for all reply queues and passes down a single address in the
ReplyDescriptorPostQueueAddress field of the IOC Init Request
Message to the firmware.
When firmware receives
Sending the this patch once agin using git send-email.
Up to now, Driver allocates a single contiguous block of memory
pool for all reply queues and passes down a single address in the
ReplyDescriptorPostQueueAddress field of the IOC Init Request
Message to the firmware.
When firmware receives
Sending the this patch once agin using git send-email.
Up to now, Driver allocates a single contiguous block of memory
pool for all reply queues and passes down a single address in the
ReplyDescriptorPostQueueAddress field of the IOC Init Request
Message to the firmware.
When firmware receives
Sending this patch once again using git send-email.
Up to now, Driver allocates a single contiguous block of memory
pool for all reply queues and passes down a single address in the
ReplyDescriptorPostQueueAddress field of the IOC Init Request
Message to the firmware.
When firmware receives
On Tue, 2014-08-12 at 14:54 +0530, Sreekanth Reddy wrote:
So, the proposal is to allocate memory independently for each
Reply Queue and pass down all of the addresses to the firmware.
Then the firmware will just take each address and program the value
into the correct register.
trivial note
On Tue, Aug 12, 2014 at 3:07 PM, Joe Perches j...@perches.com wrote:
On Tue, 2014-08-12 at 14:54 +0530, Sreekanth Reddy wrote:
So, the proposal is to allocate memory independently for each
Reply Queue and pass down all of the addresses to the firmware.
Then the firmware will just take each
> "Sreekanth" == Sreekanth Reddy writes:
Sreekanth> Please let me known any further changes are required so that
Sreekanth> I can send this patch once again with git send-email.
I'm OK with the latest iteration.
--
Martin K. Petersen Oracle Linux Engineering
--
To unsubscribe from
_flag);
>>> +static int
>>> +_base_wait_for_doorbell_ack(struct MPT2SAS_ADAPTER *ioc, int timeout,
>>> +int sleep_flag);
>>> +static int
>>> +_base_wait_for_doorbell_not_used(struct MPT2SAS_ADAPTER *ioc, int
>>> timeou
Sreekanth == Sreekanth Reddy sreekanth.re...@avagotech.com writes:
Sreekanth Please let me known any further changes are required so that
Sreekanth I can send this patch once again with git send-email.
I'm OK with the latest iteration.
--
Martin K. Petersen Oracle Linux Engineering
--
To
,
+ int sleep_flag);
+static int
+_base_handshake_req_reply_wait(struct MPT2SAS_ADAPTER *ioc, int
request_bytes,
+u32 *request, int reply_bytes, u16 *reply, int timeout, int
sleep_flag);
+static int
+_base_get_ioc_facts(struct MPT2SAS_ADAPTER *ioc, int sleep_flag);
Are you sure you need
h.
Thanks, Tomas
>
> Up to now, Driver allocates a single contiguous block of memory
> pool for all reply queues and passes down a single address in the
> ReplyDescriptorPostQueueAddress field of the IOC Init Request
> Message to the firmware.
>
> When firmware receives this
, Tomas
Up to now, Driver allocates a single contiguous block of memory
pool for all reply queues and passes down a single address in the
ReplyDescriptorPostQueueAddress field of the IOC Init Request
Message to the firmware.
When firmware receives this address, it will program each of the
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