> On Sat, Aug 25, 2012 at 08:00:56AM +0800, Bill Huang wrote:
> > nvpublic
> > > So what you're asking for is a feature to do what
> > > CONFIG_PM_SLEEP_SMP does, but without CONFIG_PM_SLEEP_SMP enabled?
> >
> > Yeah pretty much, I'm actually asking should we take care of this
> > since maybe not a
On Sat, Aug 25, 2012 at 08:52:21AM +0100, Russell King - ARM Linux wrote:
> On Sat, Aug 25, 2012 at 03:36:27PM +0800, Shawn Guo wrote:
> > On Fri, Aug 24, 2012 at 07:21:33PM +0100, Russell King - ARM Linux wrote:
> > > Why not just ensure that CONFIG_PM_SLEEP_SMP is enabled if your platform
> > > r
On Sat, Aug 25, 2012 at 03:36:27PM +0800, Shawn Guo wrote:
> On Fri, Aug 24, 2012 at 07:21:33PM +0100, Russell King - ARM Linux wrote:
> > Why not just ensure that CONFIG_PM_SLEEP_SMP is enabled if your platform
> > requires that the lowest CPU number be the CPU dealing with reboot?
>
> I have CON
On Fri, Aug 24, 2012 at 07:21:33PM +0100, Russell King - ARM Linux wrote:
> Why not just ensure that CONFIG_PM_SLEEP_SMP is enabled if your platform
> requires that the lowest CPU number be the CPU dealing with reboot?
I have CONFIG_PM_SLEEP_SMP enabled for imx6q, but still see the imx6q
restart h
On Sat, Aug 25, 2012 at 08:00:56AM +0800, Bill Huang wrote:
> nvpublic
> > So what you're asking for is a feature to do what CONFIG_PM_SLEEP_SMP does,
> > but without
> > CONFIG_PM_SLEEP_SMP enabled?
>
> Yeah pretty much, I'm actually asking should we take care of this since maybe
> not all plat
nvpublic
> On Fri, Aug 24, 2012 at 04:23:39PM +0800, Bill Huang wrote:
> > When doing shutdown on Tegra20/Tegra30, we need to read/write PMIC
> > registers through I2C to perform the power off sequence.
> > Unfortunately, sometimes we'll fail to shutdown due to I2C timeout on
> > Tegra20. And the c
On Fri, Aug 24, 2012 at 04:23:39PM +0800, Bill Huang wrote:
> When doing shutdown on Tegra20/Tegra30, we need to read/write PMIC
> registers through I2C to perform the power off sequence. Unfortunately,
> sometimes we'll fail to shutdown due to I2C timeout on Tegra20. And the
> cause of the timeout
Hi,
When doing shutdown on Tegra20/Tegra30, we need to read/write PMIC registers
through I2C
to perform the power off sequence. Unfortunately, sometimes we'll fail to
shutdown
due to I2C timeout on Tegra20. And the cause of the timeout is due to the CPU
which I2C
controller IRQ affined to will
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