After thinking about it for a while, I feel it difficult to image how non
shareable plus normal cacheable works for vpending table. Supposing the
shareability bits are to direct the corresponding GICR to read/write table
memory, if a vPE is first scheduled on pCPU0 with GICR0 and an VLPI is
tr
Thanks.
One more question about the cacheability of VPROPBASER, which is RaWb, while it
is RaWaWb for PROPBASER. Any special reason for this?
Heyi
On 2019/5/9 15:58, Marc Zyngier wrote:
On Thu, 09 May 2019 08:10:09 +0100,
Heyi Guo wrote:
Hi Marc,
We can see in its_vpe_schedule() the share
On Thu, 09 May 2019 08:10:09 +0100,
Heyi Guo wrote:
>
> Hi Marc,
>
> We can see in its_vpe_schedule() the shareability bits of
> GICR_VPENDBASER are set as non-shareable, But we set physical
> PENDBASER as inner-shareable. Is there any special reason for doing
> this? If it is because the vpendi
Hi Marc,
We can see in its_vpe_schedule() the shareability bits of GICR_VPENDBASER are
set as non-shareable, But we set physical PENDBASER as inner-shareable. Is
there any special reason for doing this? If it is because the vpending table is
GICR specific, why don't we do the same for physical
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