Re: Why ssse3?

2007-05-03 Thread Roland Dreier
> PNI (Prescott New Instructions) was the original engineering code name. > Unfortunately > it was added too early before the marketing name was known and then it > couldn't be > changed anymore. ... and just to make things more fun, SSE4 is sometimes called Penryn New Instructions -- PNI

Re: Why ssse3?

2007-05-03 Thread Andi Kleen
On Thursday 03 May 2007 11:02:31 Avi Kivity wrote: > Andi Kleen wrote: > > On Thursday 03 May 2007 00:56:26 Ulrich Drepper wrote: > > > >> Andi Kleen wrote: > >> > >>> Nope. SSE3 != SSSE3. The additional S means Supplemential. > >>> > >>> It's probably because the few changes didn't

Re: Why ssse3?

2007-05-03 Thread Avi Kivity
Andi Kleen wrote: On Thursday 03 May 2007 00:56:26 Ulrich Drepper wrote: Andi Kleen wrote: Nope. SSE3 != SSSE3. The additional S means Supplemential. It's probably because the few changes didn't justify a SSE4 OK, the problem is that the actual sse3 bit is misnamed. According

Re: Why ssse3?

2007-05-03 Thread Andi Kleen
On Thursday 03 May 2007 00:56:26 Ulrich Drepper wrote: > Andi Kleen wrote: > > Nope. SSE3 != SSSE3. The additional S means Supplemential. > > > > It's probably because the few changes didn't justify a SSE4 > > OK, the problem is that the actual sse3 bit is misnamed. According to > Intel's docs

Re: Why ssse3?

2007-05-03 Thread Andi Kleen
On Thursday 03 May 2007 00:56:26 Ulrich Drepper wrote: Andi Kleen wrote: Nope. SSE3 != SSSE3. The additional S means Supplemential. It's probably because the few changes didn't justify a SSE4 OK, the problem is that the actual sse3 bit is misnamed. According to Intel's docs bit 0 of

Re: Why ssse3?

2007-05-03 Thread Avi Kivity
Andi Kleen wrote: On Thursday 03 May 2007 00:56:26 Ulrich Drepper wrote: Andi Kleen wrote: Nope. SSE3 != SSSE3. The additional S means Supplemential. It's probably because the few changes didn't justify a SSE4 OK, the problem is that the actual sse3 bit is misnamed. According

Re: Why ssse3?

2007-05-03 Thread Andi Kleen
On Thursday 03 May 2007 11:02:31 Avi Kivity wrote: Andi Kleen wrote: On Thursday 03 May 2007 00:56:26 Ulrich Drepper wrote: Andi Kleen wrote: Nope. SSE3 != SSSE3. The additional S means Supplemential. It's probably because the few changes didn't justify a SSE4 OK,

Re: Why ssse3?

2007-05-03 Thread Roland Dreier
PNI (Prescott New Instructions) was the original engineering code name. Unfortunately it was added too early before the marketing name was known and then it couldn't be changed anymore. ... and just to make things more fun, SSE4 is sometimes called Penryn New Instructions -- PNI all

Re: Why ssse3?

2007-05-02 Thread H. Peter Anvin
Ulrich Drepper wrote: > Andi Kleen wrote: >> Nope. SSE3 != SSSE3. The additional S means Supplemential. >> >> It's probably because the few changes didn't justify a SSE4 > > OK, the problem is that the actual sse3 bit is misnamed. According to > Intel's docs bit 0 of ECX is "sse", the kernel

Re: Why ssse3?

2007-05-02 Thread Ulrich Drepper
Andi Kleen wrote: > Nope. SSE3 != SSSE3. The additional S means Supplemential. > > It's probably because the few changes didn't justify a SSE4 OK, the problem is that the actual sse3 bit is misnamed. According to Intel's docs bit 0 of ECX is "sse", the kernel uses "pni". Too bad. -- ➧ Ulrich

Re: Why ssse3?

2007-05-02 Thread Andi Kleen
On Thursday 03 May 2007 00:41:22 Ulrich Drepper wrote: > Note the extra 's'. We use "sse" and "sse2", but "ssse3". I assume > it's a typo. Nope. SSE3 != SSSE3. The additional S means Supplemential. It's probably because the few changes didn't justify a SSE4 -Andi - To unsubscribe from this

Re: Why ssse3?

2007-05-02 Thread Ismail Dönmez
On Thursday 03 May 2007 01:41:22 Ulrich Drepper wrote: > Note the extra 's'. We use "sse" and "sse2", but "ssse3". I assume > it's a typo. This might not be a typo see http://en.wikipedia.org/wiki/SSSE3 Regards, ismail signature.asc Description: This is a digitally signed message part.

Why ssse3?

2007-05-02 Thread Ulrich Drepper
Note the extra 's'. We use "sse" and "sse2", but "ssse3". I assume it's a typo. Signed-off-by: Ulrich Drepper <[EMAIL PROTECTED]> --- arch/i386/kernel/cpu/proc.c 2007-02-15 11:21:18.0 -0800 +++ arch/i386/kernel/cpu/proc.c-new 2007-05-02 15:31:17.0 -0700 @@ -46,7 +46,7 @@

Why ssse3?

2007-05-02 Thread Ulrich Drepper
Note the extra 's'. We use sse and sse2, but ssse3. I assume it's a typo. Signed-off-by: Ulrich Drepper [EMAIL PROTECTED] --- arch/i386/kernel/cpu/proc.c 2007-02-15 11:21:18.0 -0800 +++ arch/i386/kernel/cpu/proc.c-new 2007-05-02 15:31:17.0 -0700 @@ -46,7 +46,7 @@

Re: Why ssse3?

2007-05-02 Thread Ismail Dönmez
On Thursday 03 May 2007 01:41:22 Ulrich Drepper wrote: Note the extra 's'. We use sse and sse2, but ssse3. I assume it's a typo. This might not be a typo see http://en.wikipedia.org/wiki/SSSE3 Regards, ismail signature.asc Description: This is a digitally signed message part.

Re: Why ssse3?

2007-05-02 Thread Andi Kleen
On Thursday 03 May 2007 00:41:22 Ulrich Drepper wrote: Note the extra 's'. We use sse and sse2, but ssse3. I assume it's a typo. Nope. SSE3 != SSSE3. The additional S means Supplemential. It's probably because the few changes didn't justify a SSE4 -Andi - To unsubscribe from this list: send

Re: Why ssse3?

2007-05-02 Thread Ulrich Drepper
Andi Kleen wrote: Nope. SSE3 != SSSE3. The additional S means Supplemential. It's probably because the few changes didn't justify a SSE4 OK, the problem is that the actual sse3 bit is misnamed. According to Intel's docs bit 0 of ECX is sse, the kernel uses pni. Too bad. -- ➧ Ulrich

Re: Why ssse3?

2007-05-02 Thread H. Peter Anvin
Ulrich Drepper wrote: Andi Kleen wrote: Nope. SSE3 != SSSE3. The additional S means Supplemential. It's probably because the few changes didn't justify a SSE4 OK, the problem is that the actual sse3 bit is misnamed. According to Intel's docs bit 0 of ECX is sse, the kernel uses pni. Too