tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: d3590ebf6f91350192737dd1d1b219c05277f067 commit: 670d0a4b10704667765f7d18f7592993d02783aa sparse: use identifiers to define address spaces date: 6 weeks ago config: riscv-randconfig-s031-20200729 (attached as .config) compiler: riscv32-linux-gcc (GCC) 9.3.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # apt-get install sparse # sparse version: v0.6.2-97-gee4aea9a-dirty git checkout 670d0a4b10704667765f7d18f7592993d02783aa # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <l...@intel.com>
sparse warnings: (new ones prefixed by >>)
drivers/clocksource/timer-riscv.c: note: in included file (through
include/linux/timex.h, include/linux/clocksource.h):
>> arch/riscv/include/asm/timex.h:42:16: sparse: sparse: cast removes address
>> space '__iomem' of expression
>> arch/riscv/include/asm/timex.h:42:16: sparse: sparse: incorrect type in
>> argument 1 (different address spaces) @@ expected void const volatile
>> [noderef] __iomem *addr @@ got unsigned int [usertype] * @@
>> arch/riscv/include/asm/timex.h:42:16: sparse: expected void const
>> volatile [noderef] __iomem *addr
arch/riscv/include/asm/timex.h:42:16: sparse: got unsigned int
[usertype] *
>> arch/riscv/include/asm/timex.h:42:16: sparse: sparse: incorrect type in
>> argument 1 (different address spaces) @@ expected void const volatile
>> [noderef] __iomem *addr @@ got unsigned int [usertype] * @@
>> arch/riscv/include/asm/timex.h:42:16: sparse: expected void const
>> volatile [noderef] __iomem *addr
arch/riscv/include/asm/timex.h:42:16: sparse: got unsigned int
[usertype] *
>> arch/riscv/include/asm/timex.h:42:16: sparse: sparse: incorrect type in
>> argument 1 (different address spaces) @@ expected void const volatile
>> [noderef] __iomem *addr @@ got unsigned int [usertype] * @@
>> arch/riscv/include/asm/timex.h:42:16: sparse: expected void const
>> volatile [noderef] __iomem *addr
arch/riscv/include/asm/timex.h:42:16: sparse: got unsigned int
[usertype] *
>> arch/riscv/include/asm/timex.h:42:16: sparse: sparse: incorrect type in
>> argument 1 (different address spaces) @@ expected void const volatile
>> [noderef] __iomem *addr @@ got unsigned int [usertype] * @@
>> arch/riscv/include/asm/timex.h:42:16: sparse: expected void const
>> volatile [noderef] __iomem *addr
arch/riscv/include/asm/timex.h:42:16: sparse: got unsigned int
[usertype] *
>> arch/riscv/include/asm/timex.h:42:16: sparse: sparse: incorrect type in
>> argument 1 (different address spaces) @@ expected void const volatile
>> [noderef] __iomem *addr @@ got unsigned int [usertype] * @@
>> arch/riscv/include/asm/timex.h:42:16: sparse: expected void const
>> volatile [noderef] __iomem *addr
arch/riscv/include/asm/timex.h:42:16: sparse: got unsigned int
[usertype] *
>> arch/riscv/include/asm/timex.h:42:16: sparse: sparse: incorrect type in
>> argument 1 (different address spaces) @@ expected void const volatile
>> [noderef] __iomem *addr @@ got unsigned int [usertype] * @@
>> arch/riscv/include/asm/timex.h:42:16: sparse: expected void const
>> volatile [noderef] __iomem *addr
arch/riscv/include/asm/timex.h:42:16: sparse: got unsigned int
[usertype] *
>> arch/riscv/include/asm/timex.h:42:16: sparse: sparse: incorrect type in
>> argument 1 (different address spaces) @@ expected void const volatile
>> [noderef] __iomem *addr @@ got unsigned int [usertype] * @@
>> arch/riscv/include/asm/timex.h:42:16: sparse: expected void const
>> volatile [noderef] __iomem *addr
arch/riscv/include/asm/timex.h:42:16: sparse: got unsigned int
[usertype] *
>> arch/riscv/include/asm/timex.h:42:16: sparse: sparse: incorrect type in
>> argument 1 (different address spaces) @@ expected void const volatile
>> [noderef] __iomem *addr @@ got unsigned int [usertype] * @@
>> arch/riscv/include/asm/timex.h:42:16: sparse: expected void const
>> volatile [noderef] __iomem *addr
arch/riscv/include/asm/timex.h:42:16: sparse: got unsigned int
[usertype] *
vim +/__iomem +42 arch/riscv/include/asm/timex.h
6d60b6ee0c9777b Palmer Dabbelt 2017-07-10 31
6d60b6ee0c9777b Palmer Dabbelt 2017-07-10 32 #ifdef CONFIG_64BIT
2f12dbf190d97dc Christoph Hellwig 2019-08-21 33 static inline u64
get_cycles64(void)
6d60b6ee0c9777b Palmer Dabbelt 2017-07-10 34 {
6d60b6ee0c9777b Palmer Dabbelt 2017-07-10 35 return get_cycles();
6d60b6ee0c9777b Palmer Dabbelt 2017-07-10 36 }
2f12dbf190d97dc Christoph Hellwig 2019-08-21 37 #else /* CONFIG_64BIT */
2f12dbf190d97dc Christoph Hellwig 2019-08-21 38 static inline u32
get_cycles_hi(void)
2f12dbf190d97dc Christoph Hellwig 2019-08-21 39 {
4f9bbcefa142862 Christoph Hellwig 2019-10-28 40 if
(IS_ENABLED(CONFIG_RISCV_SBI))
2f12dbf190d97dc Christoph Hellwig 2019-08-21 41 return
csr_read(CSR_TIMEH);
4f9bbcefa142862 Christoph Hellwig 2019-10-28 @42 return
mmio_get_cycles_hi();
2f12dbf190d97dc Christoph Hellwig 2019-08-21 43 }
2f12dbf190d97dc Christoph Hellwig 2019-08-21 44
:::::: The code at line 42 was first introduced by commit
:::::: 4f9bbcefa142862782275a4b29f390ca8d8b9242 riscv: add support for MMIO
access to the timer registers
:::::: TO: Christoph Hellwig <h...@lst.de>
:::::: CC: Paul Walmsley <paul.walms...@sifive.com>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
