bandwidth monitoring event management
Includes all the core infrastructure to measure the total_bytes and
bandwidth.
We have per socket counters for both total system wide L3 external
bytes and local socket memory-controller bytes. The OS does MSR writes
to MSR_IA32_QM_EVTSEL and MSR_IA32_QM_CTR to
Includes all the core infrastructure to measure the total_bytes and
bandwidth.
We have per socket counters for both total system wide L3 external bytes
and local socket memory-controller bytes. The OS does MSR writes to
MSR_IA32_QM_EVTSEL and MSR_IA32_QM_CTR to read the counters and uses the
IA32_
From: Tony Luck
Includes all the core infrastructure to measure the total_bytes and
bandwidth.
We have per socket counters for both total system wide L3 external bytes
and local socket memory-controller bytes. The OS does MSR writes to
MSR_IA32_QM_EVTSEL and MSR_IA32_QM_CTR to read the counters
On Mon, 7 Mar 2016, Peter Zijlstra wrote:
On Tue, Mar 01, 2016 at 03:48:26PM -0800, Vikas Shivappa wrote:
Lot of the scheduling code was taken out from Tony's patch and a 3-4
lines of change were added in the intel_cqm_event_read. Since the timer
is no more added on every context switch this
On Tue, 8 Mar 2016, Peter Zijlstra wrote:
On Mon, Mar 07, 2016 at 11:27:26PM +, Luck, Tony wrote:
+ bytes = mbm_current->interval_bytes * MSEC_PER_SEC;
+ do_div(bytes, diff_time);
+ mbm_current->bandwidth = bytes;
+ mbm_current->inte
On Mon, Mar 07, 2016 at 11:27:26PM +, Luck, Tony wrote:
> >> + bytes = mbm_current->interval_bytes * MSEC_PER_SEC;
> >> + do_div(bytes, diff_time);
> >> + mbm_current->bandwidth = bytes;
> >> + mbm_current->interval_bytes = 0;
> >> + mbm_current->int
>> +bytes = mbm_current->interval_bytes * MSEC_PER_SEC;
>> +do_div(bytes, diff_time);
>> +mbm_current->bandwidth = bytes;
>> +mbm_current->interval_bytes = 0;
>> +mbm_current->interval_start = cur_time;
>> +}
>>> +
>> +return mbm_c
On Tue, Mar 01, 2016 at 03:48:26PM -0800, Vikas Shivappa wrote:
> Lot of the scheduling code was taken out from Tony's patch and a 3-4
> lines of change were added in the intel_cqm_event_read. Since the timer
> is no more added on every context switch this change was made.
It this here to confuse
From: Tony Luck
Includes all the core infrastructure to measure the total_bytes and
bandwidth.
We have per socket counters for both total system wide L3 external bytes
and local socket memory-controller bytes. The current b/w is calculated
for a minimum diff time(time since it was last counted)
Vikas,
On Wed, 17 Feb 2016, Vikas Shivappa wrote:
> Was wondering if you had any feedback on the MBM patches. These are almost a
> complete rewrite (the core part 3/5 from Tony Luck). The reused parts are
> mostly the declarations of datastructures. This has tried to address all your
> comments on
monitoring.
It supports both 'local bandwidth' and 'total bandwidth' monitoring for
the socket. Local bandwidth measures the amount of data sent through
the memory controller on the socket and total b/w measures the total
system bandwidth.
The tasks are associated with a Resouce Moni
bandwidth from one level of cache to another. The current patches
support L3 external bandwitch monitoring.
It supports both 'local bandwidth' and 'total bandwidth' monitoring for
the socket. Local bandwidth measures the amount of data sent through
the memory controller on the
From: Tony Luck
Includes all the core infrastructure to measure the total_bytes and
bandwidth.
We have per socket counters for both total system wide L3 external bytes
and local socket memory-controller bytes. The current b/w is calculated
for a minimum diff time(time since it was last counted) o
On Thu, 10 Sep, at 02:18:49PM, Kanaka Juvva wrote:
> > >
> > > > > } else {
> > > > > mbm_current = &mbm_total[vrmid];
> > > > > eventid = QOS_MBM_TOTAL_EVENT_ID;
> > > > > }
> > > > > rmid = tmp32;
> > > >
> > > > Why did you assign rmi
On Thu, 2015-09-10 at 14:58 +0100, Matt Fleming wrote:
> On Tue, 2015-09-08 at 18:06 +0100, Juvva, Kanaka D wrote:
> >
> > There are two aspects:
> >
> > 1) Programming MSRs
> > 2) EVENT_ATTR_STR(llc_local_bw, intel_cqm_llc_local_bw, "event=0x04");
> >
> > 1 is used for programming MSRs
> >
On Tue, 2015-09-08 at 18:06 +0100, Juvva, Kanaka D wrote:
>
> There are two aspects:
>
> 1) Programming MSRs
> 2) EVENT_ATTR_STR(llc_local_bw, intel_cqm_llc_local_bw, "event=0x04");
>
> 1 is used for programming MSRs
> 2 event attribute for perf
>
>
> For MBM_LOCAL_EVENT HW ID is 0x3. W
Sent: Wednesday, August 19, 2015 1:50 PM
>> > To: Kanaka Juvva
>> > Cc: Juvva, Kanaka D; Williamson, Glenn P; Fleming, Matt; Auld, Will;
>> Andi Kleen;
>> > LKML; Luck, Tony; Peter Zijlstra; Tejun Heo; x...@kernel.org; Ingo
>> Molnar; H.
>> > Peter A
leen;
> LKML; Luck, Tony; Peter Zijlstra; Tejun Heo; x...@kernel.org; Ingo Molnar; H.
> Peter Anvin; Shivappa, Vikas
> Subject: Re: [PATCH v3 1/2] perf,x86: add Intel Memory Bandwidth Monitoring
> (MBM) PMU
>
> On Mon, 2015-09-07 at 20:22 +0100, Juvva, Kanaka D wrote:
> >
ikas
> Subject: Re: [PATCH v3 1/2] perf,x86: add Intel Memory Bandwidth Monitoring
> (MBM) PMU
>
> On Mon, 2015-09-07 at 20:22 +0100, Juvva, Kanaka D wrote:
> > Hi Thomas,
> >
> >I'm sending updated patch(s). I have given details for each of
> > th
2015 1:50 PM
> > To: Kanaka Juvva
> > Cc: Juvva, Kanaka D; Williamson, Glenn P; Fleming, Matt; Auld, Will;
> Andi Kleen;
> > LKML; Luck, Tony; Peter Zijlstra; Tejun Heo; x...@kernel.org; Ingo
> Molnar; H.
> > Peter Anvin; Shivappa, Vikas
> > Subject: Re: [PATCH v3 1/2]
On Thu, 20 Aug 2015, Juvva, Kanaka D wrote:
> Hi Thomas,
Please do not top post and trim your replies proper.
> Acknowledged. Perhaps some discussions are required in terms of
> your questions and our solutions.
Fine with me.
> Mostly nothing was unresolved except some new things that are
> bro
olnar; H. Peter Anvin; Shivappa, Vikas
> Subject: Re: [PATCH v3 1/2] perf,x86: add Intel Memory Bandwidth
> Monitoring (MBM) PMU
>
> On Fri, 7 Aug 2015, Kanaka Juvva wrote:
> > +#define MBM_CNTR_MAX 0xff
> > +#define MBM_SOCKET_MAX 8
>
On Fri, 7 Aug 2015, Kanaka Juvva wrote:
> +#define MBM_CNTR_MAX 0xff
> +#define MBM_SOCKET_MAX 8
> +#define MBM_TIME_DELTA_MAX 1000
> +#define MBM_TIME_DELTA_MIN 100
What are these constants for and how are they determined? Pulled out
of thin air?
> +#define MBM_SCAL
.com; Shivappa, Vikas
> Subject: [PATCH v3 1/2] perf,x86: add Intel Memory Bandwidth Monitoring
> (MBM) PMU
>
> This patch adds Memory Bandwidth Monitoring events to the exitsing intel_cqm
> pmu in the Linux Kernel.
>
> Intel MBM builds on Cache Monitoring Technology (CMT) infrast
This patch adds Memory Bandwidth Monitoring events to the exitsing
intel_cqm pmu in the Linux Kernel.
Intel MBM builds on Cache Monitoring Technology (CMT) infrastructure
to allow monitoring of bandwidth from one level of the cache hierarchy
to the next - in this case focusing on the L3 cache
org;
> mi...@redhat.com; H. Peter Anvin; Shivappa, Vikas
> Subject: Re: [PATCH v2] perf,x86: add Intel Memory Bandwidth Monitoring
> (MBM) PMU
>
> On Tue, 21 Jul 2015, Kanaka Juvva wrote:
> > diff --git a/arch/x86/kernel/cpu/perf_event_intel_cqm.c
> > b/arch/x86/kernel/
On Tue, 21 Jul 2015, Kanaka Juvva wrote:
> diff --git a/arch/x86/kernel/cpu/perf_event_intel_cqm.c
> b/arch/x86/kernel/cpu/perf_event_intel_cqm.c
> index 1880761..dc1ce58 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel_cqm.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel_cqm.c
> @@ -12,10 +12,20
This patch adds Memory Bandwidth Monitoring events to the exitsing
intel_cqm pmu in the Linux Kernel.
Intel MBM builds on Cache Monitoring Technology (CMT) infrastructure
to allow monitoring of bandwidth from one level of the cache hierarchy
to the next - in this case focusing on the L3 cache
This patch adds Memory Bandwidth Monitoring events to the exitsing
intel_cqm pmu in the Linux Kernel.
Intel MBM builds on Cache Monitoring Technology (CMT) infrastructure
to allow monitoring of bandwidth from one level of the cache hierarchy
to the next - in this case focusing on the L3 cache
.com;
> jacob.w.s...@gmail.com; Brandewie, Dirk J; Shivappa, Vikas; Verplanke, Edwin;
> Kantecki, Tomasz
> Subject: [PATCH v1 1/2] perf,x86: add Intel Memory Bandwidth Monitoring
> (MBM) PMU
>
> This patch adds Memory Bandwidth Monitoring events to the exitsing intel_cqm
> pmu
This patch adds Memory Bandwidth Monitoring events to the exitsing
intel_cqm pmu in the Linux Kernel.
Intel MBM builds on Cache Monitoring Technology (CMT) infrastructure
to allow monitoring of bandwidth from one level of the cache hierarchy
to the next - in this case focusing on the L3 cache
On Sun, Oct 15, 2000 at 04:35:13AM -0500, Brian Parris wrote:
> I apologise if this is the wrong place for this, but i've been searching for
Well... the list is about kernel develoment, so it is a bit off-topic.
> 3 weeks for a way to record the bandwidth used by each user under 2.2.17, i
> know
I apologise if this is the wrong place for this, but i've been searching for
3 weeks for a way to record the bandwidth used by each user under 2.2.17, i
know there are ways to record bandwidth used by webpage hits but i also want
to monitor bandwidth used by any program the user has running, if an
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