On Thu, Nov 5, 2015 at 7:43 AM, Jean-Michel Hautbois
wrote:
>
> Le 5 nov. 2015 05:23, "Jon Nettleton" a écrit :
>>
>> On Wed, Nov 4, 2015 at 8:33 PM, Jean-Michel Hautbois
>> wrote:
>> > 2015-11-04 18:04 GMT+01:00 Jon Nettleton :
>> >> On Wed, Nov 4, 2015 at 5:52 PM, Jean-Michel Hautbois
>> >> w
On Wed, Nov 4, 2015 at 8:33 PM, Jean-Michel Hautbois
wrote:
> 2015-11-04 18:04 GMT+01:00 Jon Nettleton :
>> On Wed, Nov 4, 2015 at 5:52 PM, Jean-Michel Hautbois
>> wrote:
>>> Hi !
>>>
>>> I can see in FSL kernel that VPU is configurable to 352M (it defaults
>>> at 264MHz in mainline I think).
>>>
2015-11-04 18:04 GMT+01:00 Jon Nettleton :
> On Wed, Nov 4, 2015 at 5:52 PM, Jean-Michel Hautbois
> wrote:
>> Hi !
>>
>> I can see in FSL kernel that VPU is configurable to 352M (it defaults
>> at 264MHz in mainline I think).
>> In the TRM, it is even specified at 352MHz as a default frequency,
>>
On Wed, Nov 4, 2015 at 5:52 PM, Jean-Michel Hautbois
wrote:
> Hi !
>
> I can see in FSL kernel that VPU is configurable to 352M (it defaults
> at 264MHz in mainline I think).
> In the TRM, it is even specified at 352MHz as a default frequency,
> with a maximum of 540MHz.
>
> Would it be possible t
Hi !
I can see in FSL kernel that VPU is configurable to 352M (it defaults
at 264MHz in mainline I think).
In the TRM, it is even specified at 352MHz as a default frequency,
with a maximum of 540MHz.
Would it be possible to allow this clock rating modification if, for
instance, we select a perfor
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