Re: pci cacheline size / latency oddness.

2005-08-03 Thread Andi Kleen
On Mon, Aug 01, 2005 at 08:41:49PM -0400, Parag Warudkar wrote: > On Mon, 2005-08-01 at 19:35 -0400, Dave Jones wrote: > > This means we will do the wrong thing on AMD machines which have > > 64 byte cachelines. > > pcibios_init (in i386/pci/common.c, which is linked in by X86_64 PCI > code) seems

Re: pci cacheline size / latency oddness.

2005-08-03 Thread Andi Kleen
On Mon, Aug 01, 2005 at 07:35:17PM -0400, Dave Jones wrote: > During boot of todays -git, I noticed this.. > > PCI: Setting latency timer of device :00:1d.7 to 64 > > after boot, lspci shows.. > > 00:1d.7 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB2 EHCI > Controller (rev

Re: pci cacheline size / latency oddness.

2005-08-01 Thread Parag Warudkar
On Mon, 2005-08-01 at 19:35 -0400, Dave Jones wrote: > This means we will do the wrong thing on AMD machines which have > 64 byte cachelines. pcibios_init (in i386/pci/common.c, which is linked in by X86_64 PCI code) seems to do this if (c->x86 >= 6 && c->x86_vendor == X86_VENDOR_AMD)

Re: pci cacheline size / latency oddness.

2005-08-01 Thread Jeff Garzik
Dave Jones wrote: During boot of todays -git, I noticed this.. PCI: Setting latency timer of device :00:1d.7 to 64 after boot, lspci shows.. 00:1d.7 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller (rev 02) (prog-if 20 [EHCI]) Subsystem: Dell: Unknown device

pci cacheline size / latency oddness.

2005-08-01 Thread Dave Jones
During boot of todays -git, I noticed this.. PCI: Setting latency timer of device :00:1d.7 to 64 after boot, lspci shows.. 00:1d.7 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller (rev 02) (prog-if 20 [EHCI]) Subsystem: Dell: Unknown device 0169 Flags: bus mast