Re: pciehp is broken from 4.10-rc1

2017-02-08 Thread Bjorn Helgaas
On Mon, Feb 06, 2017 at 10:35:28PM +0100, Lukas Wunner wrote: > On Mon, Feb 06, 2017 at 12:37:06PM +0200, Mika Westerberg wrote: > > On Sun, Feb 05, 2017 at 08:34:54AM +0100, Lukas Wunner wrote: > > > @Mika, Rafael: Are you aware of Skylake machines with unreliable link > > > training, or perhaps

Re: pciehp is broken from 4.10-rc1

2017-02-08 Thread Bjorn Helgaas
On Mon, Feb 06, 2017 at 10:35:28PM +0100, Lukas Wunner wrote: > On Mon, Feb 06, 2017 at 12:37:06PM +0200, Mika Westerberg wrote: > > On Sun, Feb 05, 2017 at 08:34:54AM +0100, Lukas Wunner wrote: > > > @Mika, Rafael: Are you aware of Skylake machines with unreliable link > > > training, or perhaps

Re: pciehp is broken from 4.10-rc1

2017-02-08 Thread Erik Veijola
On Mon, Feb 06, 2017 at 10:35:28PM +0100, Lukas Wunner wrote: > On Mon, Feb 06, 2017 at 12:37:06PM +0200, Mika Westerberg wrote: > > On Sun, Feb 05, 2017 at 08:34:54AM +0100, Lukas Wunner wrote: > > > @Mika, Rafael: Are you aware of Skylake machines with unreliable link > > > training, or perhaps

Re: pciehp is broken from 4.10-rc1

2017-02-08 Thread Erik Veijola
On Mon, Feb 06, 2017 at 10:35:28PM +0100, Lukas Wunner wrote: > On Mon, Feb 06, 2017 at 12:37:06PM +0200, Mika Westerberg wrote: > > On Sun, Feb 05, 2017 at 08:34:54AM +0100, Lukas Wunner wrote: > > > @Mika, Rafael: Are you aware of Skylake machines with unreliable link > > > training, or perhaps

Re: pciehp is broken from 4.10-rc1

2017-02-06 Thread Lukas Wunner
On Mon, Feb 06, 2017 at 12:37:06PM +0200, Mika Westerberg wrote: > On Sun, Feb 05, 2017 at 08:34:54AM +0100, Lukas Wunner wrote: > > @Mika, Rafael: Are you aware of Skylake machines with unreliable link > > training, or perhaps errata of Skylake chips related to link training > > on hotplug ports?

Re: pciehp is broken from 4.10-rc1

2017-02-06 Thread Lukas Wunner
On Mon, Feb 06, 2017 at 12:37:06PM +0200, Mika Westerberg wrote: > On Sun, Feb 05, 2017 at 08:34:54AM +0100, Lukas Wunner wrote: > > @Mika, Rafael: Are you aware of Skylake machines with unreliable link > > training, or perhaps errata of Skylake chips related to link training > > on hotplug ports?

Re: pciehp is broken from 4.10-rc1

2017-02-06 Thread Bjorn Helgaas
On Sun, Feb 05, 2017 at 08:34:54AM +0100, Lukas Wunner wrote: > On Sat, Feb 04, 2017 at 08:22:59PM -0800, Yinghai Lu wrote: > > On Sat, Feb 4, 2017 at 3:34 PM, Lukas Wunner wrote: > > > On Sat, Feb 04, 2017 at 01:44:34PM -0800, Yinghai Lu wrote: > > >> On Sat, Feb 4, 2017 at

Re: pciehp is broken from 4.10-rc1

2017-02-06 Thread Bjorn Helgaas
On Sun, Feb 05, 2017 at 08:34:54AM +0100, Lukas Wunner wrote: > On Sat, Feb 04, 2017 at 08:22:59PM -0800, Yinghai Lu wrote: > > On Sat, Feb 4, 2017 at 3:34 PM, Lukas Wunner wrote: > > > On Sat, Feb 04, 2017 at 01:44:34PM -0800, Yinghai Lu wrote: > > >> On Sat, Feb 4, 2017 at 10:56 AM, Lukas

Re: pciehp is broken from 4.10-rc1

2017-02-06 Thread Rafael J. Wysocki
On Monday, February 06, 2017 12:37:06 PM Mika Westerberg wrote: > On Sun, Feb 05, 2017 at 08:34:54AM +0100, Lukas Wunner wrote: > > > sca05-0a81fd8d:~ # echo 1 > /sys/bus/pci/slots/11/power > > > [ 375.376609] pci_hotplug: power_write_file: power = 1 > > > [ 375.382175] pciehp

Re: pciehp is broken from 4.10-rc1

2017-02-06 Thread Rafael J. Wysocki
On Monday, February 06, 2017 12:37:06 PM Mika Westerberg wrote: > On Sun, Feb 05, 2017 at 08:34:54AM +0100, Lukas Wunner wrote: > > > sca05-0a81fd8d:~ # echo 1 > /sys/bus/pci/slots/11/power > > > [ 375.376609] pci_hotplug: power_write_file: power = 1 > > > [ 375.382175] pciehp

Re: pciehp is broken from 4.10-rc1

2017-02-06 Thread Mika Westerberg
On Sun, Feb 05, 2017 at 08:34:54AM +0100, Lukas Wunner wrote: > > sca05-0a81fd8d:~ # echo 1 > /sys/bus/pci/slots/11/power > > [ 375.376609] pci_hotplug: power_write_file: power = 1 > > [ 375.382175] pciehp :b3:00.0:pcie004: pciehp_get_power_status: > > SLOTCTRL a8 value read 17f1 > > [

Re: pciehp is broken from 4.10-rc1

2017-02-06 Thread Mika Westerberg
On Sun, Feb 05, 2017 at 08:34:54AM +0100, Lukas Wunner wrote: > > sca05-0a81fd8d:~ # echo 1 > /sys/bus/pci/slots/11/power > > [ 375.376609] pci_hotplug: power_write_file: power = 1 > > [ 375.382175] pciehp :b3:00.0:pcie004: pciehp_get_power_status: > > SLOTCTRL a8 value read 17f1 > > [

Re: pciehp is broken from 4.10-rc1

2017-02-04 Thread Lukas Wunner
On Sat, Feb 04, 2017 at 08:22:59PM -0800, Yinghai Lu wrote: > On Sat, Feb 4, 2017 at 3:34 PM, Lukas Wunner wrote: > > On Sat, Feb 04, 2017 at 01:44:34PM -0800, Yinghai Lu wrote: > >> On Sat, Feb 4, 2017 at 10:56 AM, Lukas Wunner wrote: > >> > On Sat, Feb 04,

Re: pciehp is broken from 4.10-rc1

2017-02-04 Thread Lukas Wunner
On Sat, Feb 04, 2017 at 08:22:59PM -0800, Yinghai Lu wrote: > On Sat, Feb 4, 2017 at 3:34 PM, Lukas Wunner wrote: > > On Sat, Feb 04, 2017 at 01:44:34PM -0800, Yinghai Lu wrote: > >> On Sat, Feb 4, 2017 at 10:56 AM, Lukas Wunner wrote: > >> > On Sat, Feb 04, 2017 at 09:12:54AM +0100, Lukas

Re: pciehp is broken from 4.10-rc1

2017-02-04 Thread Yinghai Lu
On Sat, Feb 4, 2017 at 8:22 PM, Yinghai Lu wrote: > On Sat, Feb 4, 2017 at 3:34 PM, Lukas Wunner wrote: >> On Sat, Feb 04, 2017 at 01:44:34PM -0800, Yinghai Lu wrote: >>> On Sat, Feb 4, 2017 at 10:56 AM, Lukas Wunner wrote: >>> > On Sat, Feb

Re: pciehp is broken from 4.10-rc1

2017-02-04 Thread Yinghai Lu
On Sat, Feb 4, 2017 at 8:22 PM, Yinghai Lu wrote: > On Sat, Feb 4, 2017 at 3:34 PM, Lukas Wunner wrote: >> On Sat, Feb 04, 2017 at 01:44:34PM -0800, Yinghai Lu wrote: >>> On Sat, Feb 4, 2017 at 10:56 AM, Lukas Wunner wrote: >>> > On Sat, Feb 04, 2017 at 09:12:54AM +0100, Lukas Wunner wrote: >>>

Re: pciehp is broken from 4.10-rc1

2017-02-04 Thread Yinghai Lu
On Sat, Feb 4, 2017 at 3:34 PM, Lukas Wunner wrote: > On Sat, Feb 04, 2017 at 01:44:34PM -0800, Yinghai Lu wrote: >> On Sat, Feb 4, 2017 at 10:56 AM, Lukas Wunner wrote: >> > On Sat, Feb 04, 2017 at 09:12:54AM +0100, Lukas Wunner wrote: >> > Section 6.7.3.4 of

Re: pciehp is broken from 4.10-rc1

2017-02-04 Thread Yinghai Lu
On Sat, Feb 4, 2017 at 3:34 PM, Lukas Wunner wrote: > On Sat, Feb 04, 2017 at 01:44:34PM -0800, Yinghai Lu wrote: >> On Sat, Feb 4, 2017 at 10:56 AM, Lukas Wunner wrote: >> > On Sat, Feb 04, 2017 at 09:12:54AM +0100, Lukas Wunner wrote: >> > Section 6.7.3.4 of the PCIe Base spec seems to support

Re: pciehp is broken from 4.10-rc1

2017-02-03 Thread Bjorn Helgaas
[+cc Mika, linux-kernel] On Thu, Feb 02, 2017 at 08:11:48PM -0800, Yinghai Lu wrote: > 4.9 is working, > ... > After reverting > > From 68db9bc814362e7f24371c27d12a4f34477d9356 Mon Sep 17 00:00:00 2001 > From: Lukas Wunner > Date: Fri, 28 Oct 2016 10:52:06 +0200 > Subject:

Re: pciehp is broken from 4.10-rc1

2017-02-03 Thread Bjorn Helgaas
[+cc Mika, linux-kernel] On Thu, Feb 02, 2017 at 08:11:48PM -0800, Yinghai Lu wrote: > 4.9 is working, > ... > After reverting > > From 68db9bc814362e7f24371c27d12a4f34477d9356 Mon Sep 17 00:00:00 2001 > From: Lukas Wunner > Date: Fri, 28 Oct 2016 10:52:06 +0200 > Subject: PCI: pciehp: Add