On 05/09/2018 06:40 PM, Tudor Ambarus wrote:
>
> On 05/07/2018 08:14 PM, Marek Vasut wrote:
>> But indeed there are -- to my knowledge -- no flashes with interleaved
>> erase blocks. And yes, there could be improvement in erasing exactly the
>> required chunk of flash with a fitting opcode:)
>
>
On 05/07/2018 08:14 PM, Marek Vasut wrote:
But indeed there are -- to my knowledge -- no flashes with interleaved
erase blocks. And yes, there could be improvement in erasing exactly the
required chunk of flash with a fitting opcode:)
Thanks Marek.
Other improvement would be to minimize the a
On 05/07/2018 07:11 PM, Tudor Ambarus wrote:
> Hi, Marek, all,
>
> I'm studying Cyrille's patch for non-uniform SPI NOR flash memories:
> https://lkml.org/lkml/2017/4/15/70.
>
> It's not clear to me whether interleaved regions are possible or not. I
> read the JEDEC Standard No. 216B and it looks
Hi, Marek, all,
I'm studying Cyrille's patch for non-uniform SPI NOR flash memories:
https://lkml.org/lkml/2017/4/15/70.
It's not clear to me whether interleaved regions are possible or not. I
read the JEDEC Standard No. 216B and it looks like each region is well
delimited, there is no such thin
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