[RFC PATCH 01/12] dt-bindings: clock: Add license and reformat Exynos5410 clock IDs

Add license and copyrights (file introduced in 2014) to header with Exynos5410 clock IDs. Additionally reformat it to improve readability. Signed-off-by: Krzysztof Kozlowski --- include/dt-bindings/clock/exynos5410.h | 54 -- 1 file changed, 32

[RFC PATCH 01/12] dt-bindings: clock: Add license and reformat Exynos5410 clock IDs

Add license and copyrights (file introduced in 2014) to header with Exynos5410 clock IDs. Additionally reformat it to improve readability. Signed-off-by: Krzysztof Kozlowski --- include/dt-bindings/clock/exynos5410.h | 54 -- 1 file changed, 32 insertions(+), 22

[PATCH 0/2] mtd: nand: omap2: Add EDMA support for NAND DMA prefetch

This patchset includes the required patches to enable NAND DMA prefetch support when using the EDMA. This patchset depends on my previous patchset to enable NAND DMA prefetch using the SDMA and Roger's GPMC and NAND rework. Both of these patchsets are apart of Boris' NAND next patch. Therefore,

[PATCH 2/2] ARM: OMAP2+: Update GPMC and NAND DT binding documentation

From: "Cooper Jr., Franklin" Add additional details to the GPMC NAND documentation to clarify what is needed to enable NAND DMA prefetch. Signed-off-by: Franklin S Cooper Jr Acked-by: Rob Herring ---

[PATCH 0/2] mtd: nand: omap2: Add EDMA support for NAND DMA prefetch

This patchset includes the required patches to enable NAND DMA prefetch support when using the EDMA. This patchset depends on my previous patchset to enable NAND DMA prefetch using the SDMA and Roger's GPMC and NAND rework. Both of these patchsets are apart of Boris' NAND next patch. Therefore,

[PATCH 2/2] ARM: OMAP2+: Update GPMC and NAND DT binding documentation

From: "Cooper Jr., Franklin" Add additional details to the GPMC NAND documentation to clarify what is needed to enable NAND DMA prefetch. Signed-off-by: Franklin S Cooper Jr Acked-by: Rob Herring --- Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt | 7 ++-

[PATCH 1/2] mtd: nand: omap2: Support parsing dma channel information from DT

From: "Cooper Jr., Franklin" Switch from dma_request_channel to allow passing dma channel information from DT rather than hardcoding a value. Also provide a handle to the GPMC's dev so it can be used to parse the DMA channel information within the GPMC's DT node. Signed-off-by:

Re: [PATCH] kasan: improve double-free detection

On Tue, May 3, 2016 at 11:24 AM, Luruo, Kuthonuzo wrote: >> >> We can use per-header lock by setting status to KASAN_STATE_LOCKED. A >> thread can CAS any status to KASAN_STATE_LOCKED which means that it >> locked the header. If any thread tried to modify/read the status

[PATCH 1/2] mtd: nand: omap2: Support parsing dma channel information from DT

From: "Cooper Jr., Franklin" Switch from dma_request_channel to allow passing dma channel information from DT rather than hardcoding a value. Also provide a handle to the GPMC's dev so it can be used to parse the DMA channel information within the GPMC's DT node. Signed-off-by: Franklin S

Re: [PATCH] kasan: improve double-free detection

On Tue, May 3, 2016 at 11:24 AM, Luruo, Kuthonuzo wrote: >> >> We can use per-header lock by setting status to KASAN_STATE_LOCKED. A >> thread can CAS any status to KASAN_STATE_LOCKED which means that it >> locked the header. If any thread tried to modify/read the status and >> the status is

Re: [PATCH v2 2/3] ARM: DRA7x: dts: Update the OSC_32K_CLK frequency

On 05/03/2016 12:32 PM, Tero Kristo wrote: > Personally I would not recommend using this clock for any timing sensitive > applications. May I ask why you are interested in the exact clock rate of this > clock anyway? I'm not interested in using this clock and I'm not sure how anyone would use

Re: [PATCH v2 2/3] ARM: DRA7x: dts: Update the OSC_32K_CLK frequency

On 05/03/2016 12:32 PM, Tero Kristo wrote: > Personally I would not recommend using this clock for any timing sensitive > applications. May I ask why you are interested in the exact clock rate of this > clock anyway? I'm not interested in using this clock and I'm not sure how anyone would use

[PATCH v2] drm/vc4: Return -EBUSY if there's already a pending flip event.

From: Robert Foss As per the documentation in drm_crtc.h, atomic_commit should return -EBUSY if an asycnhronous update is requested and there is an earlier update pending. Note: docs cited here are drm_crtc.h, and the whole quote is: * - -EBUSY, if an

[PATCH v2] drm/vc4: Return -EBUSY if there's already a pending flip event.

From: Robert Foss As per the documentation in drm_crtc.h, atomic_commit should return -EBUSY if an asycnhronous update is requested and there is an earlier update pending. Note: docs cited here are drm_crtc.h, and the whole quote is: * - -EBUSY, if an asynchronous updated is requested and

[PATCH v2] x86/efi-bgrt: Switch all pr_err() to pr_notice() for invalid BGRT

The promise of pretty boot splashes from firmware via BGRT was at best only that; a promise. The kernel diligently checks to make sure the BGRT data firmware gives it is valid, and dutifully warns the user when it isn't. However, it does so via the pr_err log level which seems unnecessary. The

[PATCH v2] x86/efi-bgrt: Switch all pr_err() to pr_notice() for invalid BGRT

The promise of pretty boot splashes from firmware via BGRT was at best only that; a promise. The kernel diligently checks to make sure the BGRT data firmware gives it is valid, and dutifully warns the user when it isn't. However, it does so via the pr_err log level which seems unnecessary. The

Re: [PATCH RESEND] x86/asm/entry/32: simplify pushes of zeroed pt_regs->REGs

On Mon, May 2, 2016 at 10:56 AM, Denys Vlasenko wrote: > Use of a temporary R8 register here seems to be unnecessary. > > "push %r8" is a two-byte insn (it needs REX prefix to specify R8), > "push $0" is two-byte too. It seems just using the latter would be > no worse. > >

Re: [PATCH RESEND] x86/asm/entry/32: simplify pushes of zeroed pt_regs->REGs

On Mon, May 2, 2016 at 10:56 AM, Denys Vlasenko wrote: > Use of a temporary R8 register here seems to be unnecessary. > > "push %r8" is a two-byte insn (it needs REX prefix to specify R8), > "push $0" is two-byte too. It seems just using the latter would be > no worse. > > Thus, code had an

[PATCH 00/27] coresight: next v4.6-rc6

Good morning Greg, Here's the other wave of CoreSight enhancement that I would like so see going in for the 4.7 cycle. The set applies cleanly on your current 'char-misc-next' (0a19f129d71f) branch. Get back to me if you have any concerns. Thanks, Mathieu Alexander Shishkin (1): stm class:

[PATCH 00/27] coresight: next v4.6-rc6

Good morning Greg, Here's the other wave of CoreSight enhancement that I would like so see going in for the 4.7 cycle. The set applies cleanly on your current 'char-misc-next' (0a19f129d71f) branch. Get back to me if you have any concerns. Thanks, Mathieu Alexander Shishkin (1): stm class:

[PATCH 03/27] stm class: Support devices that override software assigned masters

From: Alexander Shishkin Some STM devices adjust software assigned master numbers depending on the trace source and its runtime state and whatnot. This patch adds a sysfs attribute to inform the trace-side software that master numbers assigned to software

Re: [PATCH] procfs: fixes pthread cross-thread naming if !PR_DUMPABLE

On Tue, May 3, 2016 at 10:25 AM, Janis Danisevskis wrote: > > > On 26/04/16 21:14, Kees Cook wrote: >> >> On Tue, Apr 26, 2016 at 10:20 AM, Janis Danisevskis >> wrote: >>> >>> The PR_DUMPABLE flag causes the pid related paths of the >>> proc file system to

Re: [PATCH] kasan: improve double-free detection

On Tue, May 3, 2016 at 9:53 AM, Luruo, Kuthonuzo wrote: >> I missed that Alexander already landed patches that reduce header size >> to 16 bytes. >> It is not OK to increase them again. Please leave state as bitfield >> and update it with CAS (if we introduce helper

[PATCH 01/27] coresight: no need to do the forced type conversion

From: lipengcheng activated and enable are already unsigned type, no need to change them to unsigned. Signed-off-by: Li Pengcheng Signed-off-by: Li Zhong Signed-off-by: Mathieu Poirier ---

[PATCH 03/27] stm class: Support devices that override software assigned masters

From: Alexander Shishkin Some STM devices adjust software assigned master numbers depending on the trace source and its runtime state and whatnot. This patch adds a sysfs attribute to inform the trace-side software that master numbers assigned to software sources will not match those in the STP

Re: [PATCH] procfs: fixes pthread cross-thread naming if !PR_DUMPABLE

On Tue, May 3, 2016 at 10:25 AM, Janis Danisevskis wrote: > > > On 26/04/16 21:14, Kees Cook wrote: >> >> On Tue, Apr 26, 2016 at 10:20 AM, Janis Danisevskis >> wrote: >>> >>> The PR_DUMPABLE flag causes the pid related paths of the >>> proc file system to be owned by ROOT. The implementation

Re: [PATCH] kasan: improve double-free detection

On Tue, May 3, 2016 at 9:53 AM, Luruo, Kuthonuzo wrote: >> I missed that Alexander already landed patches that reduce header size >> to 16 bytes. >> It is not OK to increase them again. Please leave state as bitfield >> and update it with CAS (if we introduce helper functions for state >>

[PATCH 01/27] coresight: no need to do the forced type conversion

From: lipengcheng activated and enable are already unsigned type, no need to change them to unsigned. Signed-off-by: Li Pengcheng Signed-off-by: Li Zhong Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

Re: [PATCH] lightnvm: pass dma address to hardware rather than pointer

On 05/03/2016 05:22 PM, Arnd Bergmann wrote: A recent change to lightnvm added code to pass a kernel pointer to the hardware, which gcc complained about: drivers/nvme/host/lightnvm.c: In function 'nvme_nvm_rqtocmd': drivers/nvme/host/lightnvm.c:472:32: error: cast from pointer to integer of

Re: [PATCH] lightnvm: pass dma address to hardware rather than pointer

On 05/03/2016 05:22 PM, Arnd Bergmann wrote: A recent change to lightnvm added code to pass a kernel pointer to the hardware, which gcc complained about: drivers/nvme/host/lightnvm.c: In function 'nvme_nvm_rqtocmd': drivers/nvme/host/lightnvm.c:472:32: error: cast from pointer to integer of

[PATCH] md: raid10: add prerequisite to run underneath dm-raid

From: Heinz Mauelshagen In case md runs underneath the dm-raid target, the mddev does not have a request queue or gendisk, thus avoid accesses to it. This patch adds two missing conditionals to the raid10 personality. Signed-of-by: Heinz Mauelshagen ---

[PATCH] md: raid10: add prerequisite to run underneath dm-raid

From: Heinz Mauelshagen In case md runs underneath the dm-raid target, the mddev does not have a request queue or gendisk, thus avoid accesses to it. This patch adds two missing conditionals to the raid10 personality. Signed-of-by: Heinz Mauelshagen --- drivers/md/raid10.c | 12

[PATCH 08/27] coresight: etm4x: add tracer ID for A72 Maia processor.

From: lipengcheng This patch adds a cellID for the ETMv4 tracer found on HiSillicon's A72 Maia processor. Signed-off-by: Li Pengcheng Signed-off-by: Li Zhong Signed-off-by: Mathieu Poirier

[PATCH 07/27] coresight: etb10: fixing the right amount of words to read

This patch rectifies the amount of words to read when the internal buffer is deemed bigger than the amount of space available in the perf ring buffer. The amount to read is set to the amount of space in the perf ring buffer rather than being subtracted by it. Reported-by: Suzuki K Poulose

[PATCH 04/27] coresight: adding path for STM device

>From a core framework point of view an STM device is a source that is treated the same way as any other tracers. Unlike tracers though STM devices are not associated with a CPU. As such it doesn't make sense to associate the path from an STM device to its sink with a per-cpu variable as it is

[PATCH 07/27] coresight: etb10: fixing the right amount of words to read

This patch rectifies the amount of words to read when the internal buffer is deemed bigger than the amount of space available in the perf ring buffer. The amount to read is set to the amount of space in the perf ring buffer rather than being subtracted by it. Reported-by: Suzuki K Poulose

[PATCH 04/27] coresight: adding path for STM device

>From a core framework point of view an STM device is a source that is treated the same way as any other tracers. Unlike tracers though STM devices are not associated with a CPU. As such it doesn't make sense to associate the path from an STM device to its sink with a per-cpu variable as it is

[PATCH 08/27] coresight: etm4x: add tracer ID for A72 Maia processor.

From: lipengcheng This patch adds a cellID for the ETMv4 tracer found on HiSillicon's A72 Maia processor. Signed-off-by: Li Pengcheng Signed-off-by: Li Zhong Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm4x.c | 5 + 1 file changed, 5 insertions(+) diff

[PATCH 11/27] coresight: tmc: waiting for TMCReady bit before programming

According to the TRM before programming the TMC in circular buffer mode (and that for any configuration, ETB, ETR, ETF), the TMCReady bit in the status register has to be set. This patch adds a check to make sure the state machine is in a state where it can be configured, and complains otherwise.

[PATCH 06/27] coresight: stm: adding driver for CoreSight STM component

From: Pratik Patel This driver adds support for the STM CoreSight IP block, allowing any system compoment (HW or SW) to log and aggregate messages via a single entity. The CoreSight STM exposes an application defined number of channels called stimulus port.

[PATCH 11/27] coresight: tmc: waiting for TMCReady bit before programming

According to the TRM before programming the TMC in circular buffer mode (and that for any configuration, ETB, ETR, ETF), the TMCReady bit in the status register has to be set. This patch adds a check to make sure the state machine is in a state where it can be configured, and complains otherwise.

[PATCH 06/27] coresight: stm: adding driver for CoreSight STM component

From: Pratik Patel This driver adds support for the STM CoreSight IP block, allowing any system compoment (HW or SW) to log and aggregate messages via a single entity. The CoreSight STM exposes an application defined number of channels called stimulus port. Configuration is done using entries

[PATCH 05/27] coresight: stm: Bindings for System Trace Macrocell

The System Trace Macrocell (STM) is an IP block falling under the CoreSight umbrella. It's main purpose it so expose stimulus channels to any system component for the purpose of information logging. Bindings for this IP block adds a couple of items to the current mandatory definition for

[PATCH 05/27] coresight: stm: Bindings for System Trace Macrocell

The System Trace Macrocell (STM) is an IP block falling under the CoreSight umbrella. It's main purpose it so expose stimulus channels to any system component for the purpose of information logging. Bindings for this IP block adds a couple of items to the current mandatory definition for

[PATCH 10/27] coresight: tmc: modifying naming convention

According to the TMC architectural state machine, the 'stopped' state is reached when bit 2 (TMCReady) of the TMC Status register turns to '1'. The code is correct but the naming convention isn't. The 'Triggered' bit occupies position '1' of the TMC Status register and has nothing to do with the

[PATCH 10/27] coresight: tmc: modifying naming convention

According to the TMC architectural state machine, the 'stopped' state is reached when bit 2 (TMCReady) of the TMC Status register turns to '1'. The code is correct but the naming convention isn't. The 'Triggered' bit occupies position '1' of the TMC Status register and has nothing to do with the

[PATCH 16/27] coresight: tmc: splitting driver in ETB/ETF and ETR components

The TMC block can operate in 3 modes (ETB, ETF and ETR) and accessed via two interfaces (sysFS and Perf). That makes 6 mode to cover, which is way too much coupling for a single file. This patch splits the original TMC driver in 2 halves, one for ETB/ETF and another one for ETR mode. A common

[PATCH 18/27] coresight: tmc: allocating memory when needed

In it's current form the TMC probe() function allocates trace buffer memory at boot time, event if coresight isn't used. This is highly inefficient since trace buffers can occupy a lot of memory that could be used otherwised. This patch allocates trace buffers on the fly, when the coresight

[PATCH 12/27] coresight: tmc: re-implementing tmc_read_prepare/unprepare() functions

In their current implementation the tmc_read_prepare/unprepare() are a lump of if/else that is difficult to read. This patch is alleviating that by using a switch statement. The latter also allows for a better control on the error path. Signed-off-by: Mathieu Poirier

[PATCH 16/27] coresight: tmc: splitting driver in ETB/ETF and ETR components

The TMC block can operate in 3 modes (ETB, ETF and ETR) and accessed via two interfaces (sysFS and Perf). That makes 6 mode to cover, which is way too much coupling for a single file. This patch splits the original TMC driver in 2 halves, one for ETB/ETF and another one for ETR mode. A common

[PATCH 18/27] coresight: tmc: allocating memory when needed

In it's current form the TMC probe() function allocates trace buffer memory at boot time, event if coresight isn't used. This is highly inefficient since trace buffers can occupy a lot of memory that could be used otherwised. This patch allocates trace buffers on the fly, when the coresight

[PATCH 12/27] coresight: tmc: re-implementing tmc_read_prepare/unprepare() functions

In their current implementation the tmc_read_prepare/unprepare() are a lump of if/else that is difficult to read. This patch is alleviating that by using a switch statement. The latter also allows for a better control on the error path. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K

[PATCH 14/27] coresight: tmc: introducing new header file

The amount of #define, enumeration and structure definition is big enough to justify moving them to a new header file. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-tmc.c | 102

[PATCH 13/27] coresight: tmc: clearly define number of transfers per burst

This patch makes the name of the define reflect the amount of data tranfers per burst, in this case 16. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-tmc.c | 4 ++-- 1 file changed, 2

[PATCH 14/27] coresight: tmc: introducing new header file

The amount of #define, enumeration and structure definition is big enough to justify moving them to a new header file. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-tmc.c | 102 +--

[PATCH 13/27] coresight: tmc: clearly define number of transfers per burst

This patch makes the name of the define reflect the amount of data tranfers per burst, in this case 16. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-tmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[PATCH 27/27] coresight: etb10: adjust read pointer only when needed

The read pointer (read_ptr) needs to be adjusted only if its value has gone beyond the length of the memory buffer. Reported-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etb10.c | 3 ++- 1 file

[PATCH 25/27] coresight: tmc: implementing TMC-ETF AUX space API

This patch implement the AUX area interfaces required to use the TMC (configured as an ETF) from the Perf sub-system. The heuristic is heavily borrowed from the ETB10 implementation. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose

[PATCH 22/27] coresight: tmc: make sysFS and Perf mode mutually exclusive

The sysFS and Perf access methods can't be allowed to interfere with one another. As such introducing guards to access functions that prevents moving forward if a TMC is already being used. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose

[PATCH 24/27] coresight: moving struct cs_buffers to header file

That way we can re-use the structure in other drivers. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-etb10.c | 20 drivers/hwtracing/coresight/coresight-priv.h |

[PATCH 26/27] coresight: configuring ETF in FIFO mode when acting as link

When part of a path but not identified as a sink, the EFT has to be configured as a link and placed in HW FIFO mode. As such when enabling a path, call the right configuration function based on the role the ETF if playing in this trace run. Signed-off-by: Mathieu Poirier

[PATCH 24/27] coresight: moving struct cs_buffers to header file

That way we can re-use the structure in other drivers. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-etb10.c | 20 drivers/hwtracing/coresight/coresight-priv.h | 20 2 files changed, 20

[PATCH 26/27] coresight: configuring ETF in FIFO mode when acting as link

When part of a path but not identified as a sink, the EFT has to be configured as a link and placed in HW FIFO mode. As such when enabling a path, call the right configuration function based on the role the ETF if playing in this trace run. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K

[PATCH 27/27] coresight: etb10: adjust read pointer only when needed

The read pointer (read_ptr) needs to be adjusted only if its value has gone beyond the length of the memory buffer. Reported-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etb10.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git

[PATCH 25/27] coresight: tmc: implementing TMC-ETF AUX space API

This patch implement the AUX area interfaces required to use the TMC (configured as an ETF) from the Perf sub-system. The heuristic is heavily borrowed from the ETB10 implementation. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose ---

[PATCH 22/27] coresight: tmc: make sysFS and Perf mode mutually exclusive

The sysFS and Perf access methods can't be allowed to interfere with one another. As such introducing guards to access functions that prevents moving forward if a TMC is already being used. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose ---

[PATCH] ARM: BCM5301X: Add DT for Luxul XAP-1510

Luxul XAP-1510 is an AP device based on BCM4708 SoC. It uses flash memory connected to the SPI controller. Signed-off-by: Dan Haab --- arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 67 ++ 2 files

Re: [PATCH net-next 5/5] net: remove dev->trans_start

kbuild test robot <l...@intel.com> wrote: > [auto build test ERROR on net-next/master] > > url: > https://github.com/0day-ci/linux/commits/Florian-Westphal/net-remove-trans_start-from-struct-net_device/20160503-234813 > config: s390-default_defconfig (attached as .conf

[PATCH 17/27] coresight: tmc: making prepare/unprepare functions generic

Dealing with HW related matters in tmc_read_prepare/unprepare becomes convoluted when many cases need to be handled distinctively. As such moving processing related to HW setup to individual driver files and keep the core driver generic. Signed-off-by: Mathieu Poirier

[PATCH 21/27] coresight: tmc: dump system memory content only when needed

Calling tmc_etf/etr_dump_hw() is required only when operating from sysFS. When working from Perf, the system memory is harvested from the AUX trace API. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose ---

[PATCH] ARM: BCM5301X: Add DT for Luxul XAP-1510

Luxul XAP-1510 is an AP device based on BCM4708 SoC. It uses flash memory connected to the SPI controller. Signed-off-by: Dan Haab --- arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 67 ++ 2 files changed, 68

Re: [PATCH net-next 5/5] net: remove dev->trans_start

kbuild test robot wrote: > [auto build test ERROR on net-next/master] > > url: > https://github.com/0day-ci/linux/commits/Florian-Westphal/net-remove-trans_start-from-struct-net_device/20160503-234813 > config: s390-default_defconfig (attached as .config) > compiler: s

[PATCH 17/27] coresight: tmc: making prepare/unprepare functions generic

Dealing with HW related matters in tmc_read_prepare/unprepare becomes convoluted when many cases need to be handled distinctively. As such moving processing related to HW setup to individual driver files and keep the core driver generic. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K

[PATCH 21/27] coresight: tmc: dump system memory content only when needed

Calling tmc_etf/etr_dump_hw() is required only when operating from sysFS. When working from Perf, the system memory is harvested from the AUX trace API. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 7 ++-

[PATCH 19/27] coresight: tmc: getting rid of multiple read access

Allowing multiple readers to access the trace data simultaniously via sysFS provides no shortage of opportunity for race condition, mandates two variable to be maintained (drvdata::read_count and drvdata::reading), makes the code complex and provide little advantages, if any. This patch

[PATCH 23/27] coresight: tmc: keep track of memory width

Accessing the HW configuration register each time the memory width is needed simply doesn't make sense. It is much more efficient to read the value once and keep a reference for later use. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose

[PATCH 20/27] coresight: tmc: adding mode of operation for link/sinks

Moving tmc_drvdata::enable to a local_t mode. That way the sink interface is aware of it's orgin and the foundation for mutual exclusion between the sysFS and Perf interface can be laid out. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose

[PATCH 19/27] coresight: tmc: getting rid of multiple read access

Allowing multiple readers to access the trace data simultaniously via sysFS provides no shortage of opportunity for race condition, mandates two variable to be maintained (drvdata::read_count and drvdata::reading), makes the code complex and provide little advantages, if any. This patch

[PATCH 23/27] coresight: tmc: keep track of memory width

Accessing the HW configuration register each time the memory width is needed simply doesn't make sense. It is much more efficient to read the value once and keep a reference for later use. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose ---

[PATCH 20/27] coresight: tmc: adding mode of operation for link/sinks

Moving tmc_drvdata::enable to a local_t mode. That way the sink interface is aware of it's orgin and the foundation for mutual exclusion between the sysFS and Perf interface can be laid out. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose ---

[PATCH 15/27] coresight: tmc: cleaning up header file

This patch first move the TMC_STS_TMCREADY_BIT and TMC_FFCR_FLUSHMAN_BIT defines to their respective section. It also removes TMC_FFCR_FLUSHMAN, since the same result can easily be obtained using the BIT() macro. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K

[PATCH 15/27] coresight: tmc: cleaning up header file

This patch first move the TMC_STS_TMCREADY_BIT and TMC_FFCR_FLUSHMAN_BIT defines to their respective section. It also removes TMC_FFCR_FLUSHMAN, since the same result can easily be obtained using the BIT() macro. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose ---

Re: [PATCH v2 2/3] ARM: DRA7x: dts: Update the OSC_32K_CLK frequency

On 03/05/16 19:43, Tony Lindgren wrote: * J.D. Schroeder [160503 06:32]: On 05/03/2016 03:16 AM, Tero Kristo wrote: On 02/05/16 20:12, J.D. Schroeder wrote: From: "J.D. Schroeder" This commit updates the OSC_32K_CLK (secure_32k_clk_src_ck)

[PATCH 09/27] coresight: tmc: adding sysFS management entries

Adding management registers that convey implementation specific characteristics. Those are useful for trace configuration and collection along with general trouble shooting. Signed-off-by: Mathieu Poirier --- .../ABI/testing/sysfs-bus-coresight-devices-tmc| 77

[PATCH 02/27] coresight: etm4x: modify q_support type

From: lipengcheng Because this operation exceed the range of boolean, so we should modify q_support to unit8 bit. drvdata->q_support = BMVAL(etmidr0, 15, 16) Signed-off-by: Li Pengcheng Signed-off-by: Li Zhong

Re: [PATCH v2 2/3] ARM: DRA7x: dts: Update the OSC_32K_CLK frequency

On 03/05/16 19:43, Tony Lindgren wrote: * J.D. Schroeder [160503 06:32]: On 05/03/2016 03:16 AM, Tero Kristo wrote: On 02/05/16 20:12, J.D. Schroeder wrote: From: "J.D. Schroeder" This commit updates the OSC_32K_CLK (secure_32k_clk_src_ck) frequency from the precise 32kHz frequency (i.e.,

[PATCH 09/27] coresight: tmc: adding sysFS management entries

Adding management registers that convey implementation specific characteristics. Those are useful for trace configuration and collection along with general trouble shooting. Signed-off-by: Mathieu Poirier --- .../ABI/testing/sysfs-bus-coresight-devices-tmc| 77 +++

[PATCH 02/27] coresight: etm4x: modify q_support type

From: lipengcheng Because this operation exceed the range of boolean, so we should modify q_support to unit8 bit. drvdata->q_support = BMVAL(etmidr0, 15, 16) Signed-off-by: Li Pengcheng Signed-off-by: Li Zhong Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm4x.h

Re: [PATCH 5/6] HSI: omap_ssi: built omap_ssi and omap_ssi_port into one module

* Sebastian Reichel [160429 19:11]: > Merge omap_ssi and omap_ssi_port into one module. This > fixes problems with module cycle dependencies introduced > by future patches. Can you please check against the hardware for the split? For reference, below is what I dumped out from

Re: [PATCH 5/6] HSI: omap_ssi: built omap_ssi and omap_ssi_port into one module

* Sebastian Reichel [160429 19:11]: > Merge omap_ssi and omap_ssi_port into one module. This > fixes problems with module cycle dependencies introduced > by future patches. Can you please check against the hardware for the split? For reference, below is what I dumped out from dm3730 for the

[PATCH 4/4] signals/sigaltstack: Change SS_AUTODISARM to (1U << 31)

Using bit 4 divides the space of available bits strangely. Use bit 31 instead so that we have a better chance of keeping flag and mode bits separate in the long run. Cc: Stas Sergeev Cc: Al Viro Cc: Aleksa Sarai Cc: Amanieu d'Antras

[PATCH 4/4] signals/sigaltstack: Change SS_AUTODISARM to (1U << 31)

Using bit 4 divides the space of available bits strangely. Use bit 31 instead so that we have a better chance of keeping flag and mode bits separate in the long run. Cc: Stas Sergeev Cc: Al Viro Cc: Aleksa Sarai Cc: Amanieu d'Antras Cc: Andrea Arcangeli Cc: Andrew Morton Cc: Andy

[PATCH 2/4] selftests/sigaltstack: Fix the sas test on old kernels

The handling for old kernels was wrong. Fix it. Reported-by: Ingo Molnar Cc: Stas Sergeev Cc: Al Viro Cc: Andrew Morton Cc: Andy Lutomirski Cc: Borislav Petkov Cc: Brian

[PATCH 1/4] signals/sigaltstack: If SS_AUTODISARM, bypass on_sig_stack

If a signal stack is set up with SS_AUTODISARM, then the kernel inherently avoids incorrectly resetting the signal stack if signals recurse: the signal stack will be reset on the first signal delivery. This means that we don't need check the stack pointer when delivering signals if SS_AUTODISARM

[PATCH 3/4] signals/sigaltstack: Report current flag bits in sigaltstack()

sigaltstack()'s reported previous state uses a somewhat odd convention, but the concept of flag bits is new, and we can do the flag bits sensibly. Specifically, let's just report them directly. This will allow saving and restoring the sigaltstack state using sigaltstack() to work correctly.

[PATCH 2/4] selftests/sigaltstack: Fix the sas test on old kernels

The handling for old kernels was wrong. Fix it. Reported-by: Ingo Molnar Cc: Stas Sergeev Cc: Al Viro Cc: Andrew Morton Cc: Andy Lutomirski Cc: Borislav Petkov Cc: Brian Gerst Cc: Denys Vlasenko Cc: H. Peter Anvin Cc: Linus Torvalds Cc: Oleg Nesterov Cc: Pavel Emelyanov Cc: Peter

[PATCH 1/4] signals/sigaltstack: If SS_AUTODISARM, bypass on_sig_stack

If a signal stack is set up with SS_AUTODISARM, then the kernel inherently avoids incorrectly resetting the signal stack if signals recurse: the signal stack will be reset on the first signal delivery. This means that we don't need check the stack pointer when delivering signals if SS_AUTODISARM

[PATCH 3/4] signals/sigaltstack: Report current flag bits in sigaltstack()

sigaltstack()'s reported previous state uses a somewhat odd convention, but the concept of flag bits is new, and we can do the flag bits sensibly. Specifically, let's just report them directly. This will allow saving and restoring the sigaltstack state using sigaltstack() to work correctly.

[PATCH 0/4] SS_AUTODISARM fixes and an ABI change

The first three are fixes IMO. The fourth changes the SS_AUTODISARM bit. I'm assuming that's okay, as the bit has existed in -tip for less than a day. Andy Lutomirski (4): signals/sigaltstack: If SS_AUTODISARM, bypass on_sig_stack selftests/sigaltstack: Fix the sas test on old kernels

[PATCH 0/4] SS_AUTODISARM fixes and an ABI change

The first three are fixes IMO. The fourth changes the SS_AUTODISARM bit. I'm assuming that's okay, as the bit has existed in -tip for less than a day. Andy Lutomirski (4): signals/sigaltstack: If SS_AUTODISARM, bypass on_sig_stack selftests/sigaltstack: Fix the sas test on old kernels

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