From: Michael Hennerich
This patch adds support for the Analog Devices / Linear Technology
LTC4306 and LTC4305 4/2 Channel I2C Bus Multiplexer/Switches.
The LTC4306 optionally provides two general purpose input/output pins
(GPIOs) that can be configured as logic
As we added USB0 route auto switching support for A64, add related
device tree parts to the A64 DTSI file (EHCI0/OHCI0 controllers and the
pmu0 memory area for PHY).
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 24
1
Commands written to the QMan software portals have a valid
bit in the "verb" field of the command that, when set with
the right value, notifies the hardware that the command is
fully written and ready to be processed.
The "verb" field should be the last one to be written in the
swp command
> Reviewed-by: Jarkko Sakkinen
>
> Peter, Andrew, anyone: Tested-by?
Sorry, i don't have the hardware. All i can give you is:
Reviewed-by: Andrew Lunn
Andrew
Hello Philipp,
On Wed, Apr 5, 2017 at 5:34 AM, Philipp Zabel wrote:
> On Wed, 2017-04-05 at 09:21 +0100, Russell King - ARM Linux wrote:
[snip]
> I think the output part is accurate, as the audio pad is an artifact of
> an unrelated change. I'm not so sure about the VBI
On Wed, 5 Apr 2017, Felipe Balbi wrote:
> >> >> --- a/drivers/usb/gadget/udc/core.c
> >> >> +++ b/drivers/usb/gadget/udc/core.c
> >> >> @@ -1273,6 +1273,7 @@ void usb_del_gadget_udc(struct usb_gadget *gadget)
> >> >> flush_work(>work);
> >> >> device_unregister(>dev);
> >> >>
* Russell King - ARM Linux [170405 07:02]:
> On Tue, Apr 04, 2017 at 09:11:52AM -0700, Tony Lindgren wrote:
> > Russell,
> >
> > * Dave Gerlach [170328 13:57]:
> > > Certain SoCs like Texas Instruments AM335x and AM437x require parts
> > > of the EMIF PM
The USB PHY of A64 contains a "pmu0" MMIO region, which contains some control
registers for the EHCI0/OHCI0 pair on A64 SoC.
This pair is not used currently in 4.11, but when enabling it in 4.12, the
MMIO region is needed.
In order to prevent device tree compatibility breakage, add this region
On Wed, Apr 05, 2017 at 03:51:52PM +0200, SF Markus Elfring wrote:
> From: Markus Elfring
> Date: Wed, 5 Apr 2017 09:43:54 +0200
>
> * A multiplication for the size determination of a memory allocation
> indicated that an array data structure should be processed.
Finn Thain wrote:
> I can see how base addresses and IO ports are relevant, but the irq
> parameter changes below don't protect the kernel image AFAICT. What's the
> rationale for those changes? I think it should be stated here.
Easier grepping for one. But I'm
toii
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Martin Parrish
Hi,
In this forth version I improved the driver based on the review from
Linus Walleij and I fixed a configuration issue with uart2. For the
record, this series adds support for the pin and gpio controllers
present on the Armada 37xx SoCs.
Each Armada 37xx SoC comes with 2 pin controllers: one
Document the device tree binding for the pin controllers found on the
Armada 37xx SoCs.
Update the binding documention of the xtal clk which is a subnode of this
syscon node.
Signed-off-by: Gregory CLEMENT
---
Dough,
This patch and the next in this set is IMHO together a generic
enhancement/cleanup,
is it something you would consider to take just as that?
I am looking at suggesting a simplified, less target specific version of this
set
to get it off my chest,
Thanks,
Knut
On Fri, 2016-09-16 at
PHY transceiver driver for QUSB2 phy controller that provides
HighSpeed functionality for DWC3 controller present on
Qualcomm chipsets.
Signed-off-by: Vivek Gautam
Reviewed-by: Stephen Boyd
---
Changes since v6:
- Dropped 'vdd-phy' from list
This patch series adds couple of PHY drivers for Qualcomm chipsets.
a) qcom-qusb2 phy driver: that provides High Speed USB functionality.
b) qcom-qmp phy driver: that is a combo phy providing support for
USB3, PCIe, UFS and few other controllers.
The patches are based on next branch of
Qualcomm chipsets have QUSB2 phy controller that provides
HighSpeed functionality for DWC3 controller.
Adding dt binding information for the same.
Signed-off-by: Vivek Gautam
Acked-by: Rob Herring
---
Changes since v6:
- Dropped 'vdd-phy-supply'
Hi,
"Gustavo A. R. Silva" writes:
> Rewrite udc_free_dma_chain() function to avoid use of pointer after free.
>
> Addresses-Coverity-ID: 1091172
> Acked-by: Michal Nazarewicz
> Reviewed-by: Greg Kroah-Hartman
>
Qualcomm SOCs have QMP phy controller that provides support
to a number of controller, viz. PCIe, UFS, and USB.
Add a new driver, based on generic phy framework, for this
phy controller.
Signed-off-by: Vivek Gautam
Tested-by: Srinivas Kandagatla
Qualcomm chipsets have QMP phy controller that provides
support to a number of controller, viz. PCIe, UFS, and USB.
Adding dt binding information for the same.
Signed-off-by: Vivek Gautam
Acked-by: Rob Herring
---
Changes since v6:
- none.
From: Colin Ian King
There seems to be a missing break on the OOO_LB_TC case, pq_id
is being assigned and then re-assigned on the fall through default
case and that seems suspect.
Detected by CoverityScan, CID#1424402 ("Missing break in switch")
Fixes: b5a9ee7cf3be1
On 04/04, Andrew Morton wrote:
>
> On Tue, 04 Apr 2017 14:47:34 -0700 bseg...@google.com wrote:
>
> > In PT_SEIZED + LISTEN mode STOP/CONT signals cause a wakeup against
> > __TASK_TRACED. If this races with the ptrace_unfreeze_traced at the end
> > of a PTRACE_LISTEN, this can wake the task
Hi,
cristian.bir...@microchip.com writes:
> From: Cristian Birsan
>
> Minor code cleanup based on feedback received on mailinglist.
>
> Signed-off-by: Cristian Birsan
> Acked-by: Nicolas Ferre
patch 1
On Wed, Apr 05, 2017 at 11:06:33AM +0200, Quentin Schulz wrote:
> From: Maxime Ripard
>
> This adds GPU thermal throttling for the Allwinner A33.
>
> Signed-off-by: Maxime Ripard
> Signed-off-by: Quentin Schulz
On Wed, Apr 05, 2017 at 11:58:41AM +0100, Russell King - ARM Linux wrote:
> On Tue, Mar 28, 2017 at 03:45:43PM +0100, Lorenzo Pieralisi wrote:
> > On Mon, Mar 27, 2017 at 08:41:10PM -0500, Bjorn Helgaas wrote:
> > > On Mon, Mar 27, 2017 at 10:49:30AM +0100, Lorenzo Pieralisi wrote:
> > > > diff
On Wed, Apr 05, 2017 at 06:48:45PM +0800, Xin Long wrote:
> On Wed, Apr 5, 2017 at 5:14 AM, Marcelo Ricardo Leitner
> wrote:
> > On Wed, Apr 05, 2017 at 01:29:19AM +0800, Xin Long wrote:
> >> On Tue, Apr 4, 2017 at 9:28 PM, Andrey Konovalov
> >>
> There seems to be a missing break on the OOO_LB_TC case, pq_id is being
> assigned and then re-assigned on the fall through default case and that
> seems suspect.
>
> Detected by CoverityScan, CID#1424402 ("Missing break in switch")
>
> Fixes: b5a9ee7cf3be1 ("qed: Revise QM cofiguration")
>
>
Brian Norris wrote:
> If we fail to reinit the FW when resetting the device (in the
> synchronous version of mwifiex_init_hw_fw() -> mwifiex_fw_dpc()),
> mwifiex_fw_dpc() will tear down the interface and free up the adapter.
> But we don't actually check for all failure
> -Original Message-
> From: Thomas Jespersen [mailto:laumann.tho...@gmail.com]
> Sent: Tuesday, April 4, 2017 3:15 PM
> To: Kershner, David A
> Cc: gre...@linuxfoundation.org; Sell, Timothy C
> ; Binder, David Anthony
>
Colin Ian King wrote:
> From: Colin Ian King
>
> trivial fix to spelling mistakes in wl1271_warning error message, change
> iligal to invalid and opperation to operation.
>
> Signed-off-by: Colin Ian King
Patch
> -Original Message-
> From: Linus Walleij [mailto:linus.wall...@linaro.org]
> Sent: 29 March 2017 04:51
> To: Han, Nandor (GE Healthcare)
> Cc: Alexandre Courbot ; Rob Herring ;
> Mark Rutland
> ;
This patchset contains devicetree parts of the EHCI0/OHCI0 controllers
on A64 SoC.
The first patch is a devicetree binding change, which has been planned
for 4.12; however, as Maxime Ripard suggested, it should go in 4.11
as it's part of the device's description.
The second patch added pmu0 regs
I'm announcing the release of the 3.16.43 kernel.
All users of the 3.16 kernel series should upgrade.
The updated 3.16.y git tree can be found at:
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git
linux-3.16.y
and can be browsed at the normal kernel.org git web
On Wed, Apr 05, 2017 at 12:27:39PM +0200, Jan Glauber wrote:
> Fix a typo that disabled the MCI interrupts using the wrong bitmask.
>
> Signed-off-by: Jan Glauber
> ---
> drivers/edac/thunderx_edac.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
From: Icenowy Zheng
Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two
controllers: one is MUSB and the other is a EHCI/OHCI pair.
When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to
tweak, like other EHCI/OHCI pairs in Allwinner SoCs.
Add
I'm announcing the release of the 3.2.88 kernel.
All users of the 3.2 kernel series should upgrade.
The updated 3.2.y git tree can be found at:
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git
linux-3.2.y
and can be browsed at the normal kernel.org git web
On Tue 04-04-17 22:57:28, Srikar Dronamraju wrote:
[...]
> For example:
> perf bench numa mem --no-data_rand_walk -p 4 -t $THREADS -G 0 -P 3072 -T 0 -l
> 50 -c -s 1000
> would call sched_setaffinity that resets the cpus_allowed mask.
>
> Cpus_allowed_list:0-55,57-63,65-71,73-79,81-87,89-175
Hi Kishon,
On Wed, Apr 5, 2017 at 4:30 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Tuesday 28 March 2017 05:57 PM, Raviteja Garimella wrote:
>> This is driver for USB DRD Phy used in Broadcom's Northstar2
>> SoC. The phy can be configured to be in Device mode or Host
>> mode
On Mon, Apr 03, 2017 at 07:44:55PM -0700, Moritz Fischer wrote:
> Xiao,
>
> few nits inline, I'll need to come back to this once I went over the
> rest of the patchset ;-)
Sure, Thanks for your comments and review. :)
>
> On Thu, Mar 30, 2017 at 08:08:04PM +0800, Wu Hao wrote:
> > From: Xiao
On Wednesday 05 April 2017 06:20 PM, Icenowy Zheng wrote:
> From: Icenowy Zheng
>
> Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two
> controllers: one is MUSB and the other is a EHCI/OHCI pair.
>
> When it's routed to EHCI/OHCI pair, it will needs a
Hi Stephen
> > From: Kuninori Morimoto
> >
> > Thus CS2000 datasheet is indicating below, this patch
> > follows it.
> >
> > WARNING: All "Reserved" registers must maintain their default
> > state to ensure proper functional operation.
> >
> >
On Wed, Apr 5, 2017 at 10:16 PM, David Howells wrote:
> From: Matthew Garrett
>
> uswsusp allows a user process to dump and then restore kernel state, which
> makes it possible to modify the running kernel. Disable this if the kernel
> is locked down.
>
On 03/08, Avaneesh Kumar Dwivedi wrote:
> diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
> index 4a0f5ea..187fc00 100644
> --- a/drivers/firmware/qcom_scm-64.c
> +++ b/drivers/firmware/qcom_scm-64.c
> @@ -358,3 +358,28 @@ int __qcom_scm_pas_mss_reset(struct device
A new function, kernel_sock_ip_overhead(), is provided
to calculate the cumulative overhead imposed by the IP
Header and IP options, if any, on a socket's payload.
The new function returns an overhead of zero for sockets
that do not belong to the IPv4 or IPv6 address families.
This is used in the
On Wed, Apr 5, 2017 at 1:27 PM, Stephen Boyd wrote:
> On 03/23, Rick Altherr wrote:
>> +
>> +static int aspeed_adc_probe(struct platform_device *pdev)
>> +{
>> + struct iio_dev *indio_dev;
>> + struct aspeed_adc_data *data;
>> + const struct aspeed_adc_model_data
On Wed, Mar 22, 2017 at 11:35:55AM +0100, Peter Zijlstra wrote:
> There's a number of 'interesting' problems, all caused by holding
> hb->lock while doing the rt_mutex_unlock() equivalient.
>
> Notably:
>
> - a PI inversion on hb->lock; and,
>
> - a DL crash because of pointer instability.
A
On Tuesday 04/04 at 23:27 -0400, Steven Rostedt wrote:
> On Wed, 5 Apr 2017 11:16:28 +0900
> Sergey Senozhatsky wrote:
>
>
> > one more thing.
> >
> > this per-console filtering ignores... the "ignore_loglevel" param.
> >
> > early_param("ignore_loglevel",
On Tuesday 04/04 at 23:30 -0400, Steven Rostedt wrote:
> On Tue, 4 Apr 2017 16:03:20 -0700
> Calvin Owens wrote:
>
> > This does the simplest possible thing: add a directory at the root of
> > sysfs that allows setting the "maxlevel" parameter for each console.
> >
> > We
On Tue, Apr 4, 2017 at 11:12 PM, Mike Galbraith wrote:
> On Tue, 2017-04-04 at 22:25 -0700, Cong Wang wrote:
>> On Tue, Apr 4, 2017 at 8:20 PM, Mike Galbraith wrote:
>> > - while (some_qdisc_is_busy(dev))
>> > - yield();
>> > +
On Wed, Mar 22, 2017 at 11:35:56AM +0100, Peter Zijlstra wrote:
> Since there's already two copies of this code, introduce a helper now
> before we get a third instance.
>
> Signed-off-by: Peter Zijlstra (Intel)
An easy one!
Reviewed-by: Darren Hart (VMware)
On Wed, Mar 29, 2017 at 6:41 PM, Kees Cook wrote:
> On Wed, Mar 29, 2017 at 3:38 PM, Andy Lutomirski wrote:
>> On Wed, Mar 29, 2017 at 11:15 AM, Kees Cook wrote:
>>> Based on PaX's x86 pax_{open,close}_kernel() implementation,
On Wed, 2017-04-05 at 21:23 +0200, Valerio Genovese wrote:
> This was reported by checkpatch.pl:
> ERROR: space required after that close brace '}'
>
> Signed-off-by: Valerio Genovese
> ---
> drivers/staging/rtl8192u/ieee80211/rtl819x_BA.h | 2 +-
> 1 file changed, 1
This changes the x86 exception for the low 1MB by reading back zeros for
RAM areas instead of blindly allowing them. (It may be possible for heap
to end up getting allocated in low 1MB RAM, and then read out, possibly
tripping hardened usercopy.)
Unfinished: this still needs mmap support.
Existing L2TP kernel code does not derive the optimal MTU for Ethernet
pseudowires and instead leaves this to a userspace L2TP daemon or
operator. If an MTU is not specified, the existing kernel code chooses
an MTU that does not take account of all tunnel header overheads, which
can lead to
On Thu, Apr 06 2017, Jeff Layton wrote:
> On Tue, 2017-04-04 at 10:09 -0700, Matthew Wilcox wrote:
>> On Tue, Apr 04, 2017 at 12:25:46PM -0400, Jeff Layton wrote:
>> > That said, I think giving more specific errors where we can is useful.
>> > When your program is erroring out and writing 'I/O
Existing L2TP kernel code does not derive the optimal MTU for Ethernet
pseudowires and instead leaves this to a userspace L2TP daemon or
operator. If an MTU is not specified, the existing kernel code chooses
an MTU that does not take account of all tunnel header overheads, which
can lead to
On 4/5/2017 12:09 AM, Arnaldo Carvalho de Melo wrote:
Em Tue, Apr 04, 2017 at 11:52:53PM +0800, Jin, Yao escreveu:
On 4/4/2017 10:18 PM, Arnaldo Carvalho de Melo wrote:
Adding the perf kernel maintainers to the CC list.
Em Fri, Mar 31, 2017 at 11:18:38PM +0800, Jin Yao escreveu:
It is
On Wed, Apr 5, 2017 at 4:57 PM, Andy Lutomirski wrote:
> On Wed, Mar 29, 2017 at 6:41 PM, Kees Cook wrote:
>> On Wed, Mar 29, 2017 at 3:38 PM, Andy Lutomirski wrote:
>>> On Wed, Mar 29, 2017 at 11:15 AM, Kees Cook
From: Long Li
Under heavy I/O, one hardware queue may be unable to dispatch any I/O to the
device layer. This poses a problem with restarting this hardware queue on I/O
finish in blk_mq_sched_restart_queues(), becaue there is nothing pending that
will finish in future on
Hi Matthew,
On Wed, Apr 5, 2017 at 3:25 PM, wrote:
>> Maybe you actually wanna bail out if you read a random other value
>> instead of what you
>> expect instead of printing a warning.
>
>
> I thought about making it an error if the version didn't match, but it
On Wed, Apr 05 2017, Matthew Wilcox wrote:
> On Wed, Apr 05, 2017 at 03:49:52PM -0400, Jeff Layton wrote:
>> > That only gives us 20 bits of counter, but I think that's enough.
>>
>> 2^20 is 1048576, which seems a little small to me.
>>
>> We may end up bumping the counter on every failed I/O.
Hi Sean,
On 04/06/2017 12:28 AM, Sean Paul wrote:
On Wed, Apr 05, 2017 at 04:29:26PM +0800, Jeffy Chen wrote:
After unbinding drm, the userspace may still has a chance to access
gem buf.
Add a sanity check for a NULL dev_private to prevent that from
happening.
I still don't understand how
On Thu, Apr 06, 2017 at 10:02:48AM +1000, NeilBrown wrote:
> If you are concerned about space in 'struct address_space', just prune
> some wastage.
I'm trying to (via wlists). still buggy though.
> The "host" field brings no value. It is only ever assigned in
> inode_init_always():
>
>
Hi Daniel,
Daniel Borkmann writes:
> On 04/04/2017 08:33 PM, Aaron Conole wrote:
>> The eBPF framework is used for more than just socket level filtering. It
>> can also provide tracing, and even change the way packets coming into the
>> system look. Most of the eBPF callable symbols are
On Thu, Apr 06, 2017 at 10:15:14AM +0930, Jonathan Woithe wrote:
> Hi Michael
>
> On Wed, Apr 05, 2017 at 09:55:34PM +0200, Micha?? K??pie?? wrote:
> > > On Wed, Apr 05, 2017 at 08:48:59AM +0200, Micha?? K??pie?? wrote:
> > > > This series introduces further changes to the way LCD backlight is
>
Hi Joe,
On 04/06/2017 10:39 AM, Joe Perches wrote:
On Thu, 2017-04-06 at 10:01 +0800, Jeffy Chen wrote:
The mail account "Yakir Yang " is no longer
valid.
Does this person still want to be involved with the kernel?
If so, perhaps a .mailmap entry would be more appropriate.
i don't think he
Symbol versioning, as in glibc, results in symbols being defined as:
@[@]
(Note that "@@" identifies a default symbol, if the symbol name
is repeated.)
perf is currently unable to deal with this, and is unable to create
user probes at such symbols:
--
$ nm
Hi all,
Today's linux-next merge of the staging tree got conflicts in:
drivers/staging/media/lirc/lirc_sasem.c
drivers/staging/media/lirc/lirc_sir.c
between commits:
e66267161971 ("[media] rc: promote lirc_sir out of staging")
51bb3fd788cb ("[media] staging: lirc_sasem: remove")
from
mlinux.lds: add missing VMLINUX_SYMBOL macros")
The latest version of this series uses new symbols provided in these
fixes. The series now cross compiles on Blackfin without errors. I have
also test compiled this series on next-20170405 for x86.
I have dropped the third patch that uses the
Provide a mechanism to check if the address of a variable is
const or ro_after_init. It mimics the existing functions that test if an
address is inside the kernel's text section.
The idea is to prevent structures that are not read-only from being
passed to functions. Other functions inside the
Implement a mechanism to check if a module's address is in
the rodata or ro_after_init sections. It mimics the existing functions
that test if an address is inside a module's text section.
Functions that take a module as an argument will be able to verify that the
module address is in a read-only
> -Original Message-
> From: Bart Van Assche [mailto:bart.vanass...@sandisk.com]
> Sent: Wednesday, April 5, 2017 5:32 PM
> To: linux-kernel@vger.kernel.org; linux-bl...@vger.kernel.org; Long Li
> ; ax...@kernel.dk
> Cc: Stephen Hemminger ; KY Srinivasan
> ; Long Li
> Subject: Re:
On 04/04/2017 09:26 AM, Arnaldo Carvalho de Melo wrote:
Em Tue, Apr 04, 2017 at 11:18:02PM +0900, Masami Hiramatsu escreveu:
On Mon, 3 Apr 2017 11:46:58 -0300
Arnaldo Carvalho de Melo wrote:
> > > But apart from those problems, I think that one should be able to ask
> > > for a versioned
On Thu, 2017-04-06 at 03:38 +, Long Li wrote:
> > -Original Message-
> > From: Bart Van Assche [mailto:bart.vanass...@sandisk.com]
> >
> > Please drop this patch. I'm working on a better solution.
>
> Thank you. Looking forward to your patch.
Hello Long,
It would help if you could
Set current email address to replace previous employers email
addresses.
Signed-off-by: Jeffy Chen
---
.mailmap | 1 +
1 file changed, 1 insertion(+)
diff --git a/.mailmap b/.mailmap
index e775f79..de0fc5b 100644
--- a/.mailmap
+++ b/.mailmap
@@ -172,6 +172,7 @@ Vlad Dogaru
Vladimir
Everything but the USER domain is the same with CONFIG_CPU_SW_DOMAIN_PAN
or not. This extracts the differences for a common DACR_INIT macro so it
is easier to make future changes (like adding the WR_RARE domain).
Signed-off-by: Kees Cook
---
arch/arm/include/asm/domain.h | 14 +++---
1
Brian Norris writes:
> nl80211 provides the NL80211_SCAN_FLAG_RANDOM_ADDR for every scan
> request that should be randomized; the absence of such a flag means we
> should not randomize. However, mwifiex was stashing the latest
> randomization request and *always* using it for future scans, even
Hi James,
After merging the scsi tree, today's linux-next build (arm
multi_v7_defconfig) produced this warning:
In file included from include/linux/list.h:8:0,
from include/linux/module.h:9,
from drivers/scsi/sd.c:35:
drivers/scsi/sd.c: In function
Hi Alan,
minor nits, inline
On Mon, Mar 13, 2017 at 04:53:32PM -0500, Alan Tull wrote:
> Add fpga_mgr_lock/unlock functions that get a mutex for
> exclusive use.
>
> of_fpga_mgr_get, fpga_mgr_get, and fpga_mgr_put no longer lock
> the FPGA manager mutex.
>
> This makes it more straightforward
On Wed, Apr 05, 2017 at 09:31:45PM -0400, Steven Rostedt wrote:
> On Wed, 5 Apr 2017 13:42:29 -0700
> "Paul E. McKenney" wrote:
>
> > > OK, do you want me to send you a patch, or should I take your patch
> > > into my tree and add this?
> >
> > Given that I don't seem to have
Hi Shuah,
[auto build test ERROR on linus/master]
[also build test ERROR on v4.11-rc5]
[cannot apply to next-20170405]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Shuah-Khan/arm-dma-fix
On Wed, Apr 05, 2017 at 10:12:24PM -0400, Steven Rostedt wrote:
> On Wed, 5 Apr 2017 10:59:25 -0700
> "Paul E. McKenney" wrote:
>
> > > > Could you please let me know if tracing happens in NMI handlers?
> > > > If so, a bit of additional code will be needed.
> > > >
> > > >
This patch moves the struct devfreq_governor from header file
to the devfreq directory because this structure is private data
and it have to be only accessed by the devfreq core.
Signed-off-by: Chanwoo Choi
---
drivers/devfreq/governor.h | 29 +
On Wed, Apr 5, 2017 at 3:35 PM, Mark Rutland wrote:
> On Wed, Apr 05, 2017 at 02:42:39PM +0530, Ganapatrao Kulkarni wrote:
>> On Tue, Apr 4, 2017 at 5:58 PM, Mark Rutland wrote:
>> > On Tue, Apr 04, 2017 at 01:06:43PM +0530, Ganapatrao Kulkarni wrote:
>> >> This is not a full event list, but a
> -Original Message-
> From: Bart Van Assche [mailto:bart.vanass...@sandisk.com]
> Sent: Wednesday, April 5, 2017 8:46 PM
> To: linux-kernel@vger.kernel.org; linux-bl...@vger.kernel.org; Long Li
> ; ax...@kernel.dk
> Cc: Stephen Hemminger ; KY Srinivasan
>
> Subject: Re: [PATCH]
Hi Alan,
first pass ... need to get back to it.
On Mon, Mar 13, 2017 at 04:53:33PM -0500, Alan Tull wrote:
> FPGA region is a layer above the FPGA manager and FPGA bridge
> frameworks. Currently, FPGA region is dependent on device tree.
> This commit separates the device tree specific code from
On Sat, Apr 1, 2017 at 1:51 AM, Brian Norris wrote:
> This reverts commit 437322ea2a36d112e20aa7282c869bf924b3a836.
>
> This above-mentioned "fix" does not actually do anything to prevent a
> race condition. It simply papers over it so that the issue doesn't
> appear.
>
> If this is a real
2017년 04월 05일 00:38에 Krzysztof Kozlowski 이(가) 쓴 글:
> On Tue, Mar 28, 2017 at 11:38 AM, Krzysztof Kozlowski wrote:
>> On Tue, Mar 28, 2017 at 11:26 AM, Inki Dae wrote:
>>> Merged.
>>
>> Hi,
>>
>> I do not see the tag (with DT patches) merged by you which I provided
>> to you before. These are
On Wed 08 Mar 10:03 PST 2017, Avaneesh Kumar Dwivedi wrote:
> This patch add scm call support to make hypervisor call to enable access
> of fw regions in ddr to mss subsystem on arm-v8 arch soc's.
>
> Signed-off-by: Avaneesh Kumar Dwivedi
> ---
> drivers/firmware/qcom_scm-64.c | 25
On 04/06/2017 12:57 AM, Andy Shevchenko wrote:
On Wed, Apr 5, 2017 at 11:20 PM, Aleksey Makarov
wrote:
If a console was specified by ACPI SPCR table _and_ command line
parameters like "console=ttyAMA0" _and_ "earlycon" were specified,
then log messages appear twice.
The root cause is that
Hi Srinivas,
I have checked the patch dose not meets my requirement for ISH.
With this patch sensor properties still losing after resume from S3.
BR
Song Hongyan
-Original Message-
From: Srinivas Pandruvada [mailto:srinivas.pandruv...@linux.intel.com]
Sent: Wednesday, April 5,
On Thu, Apr 06, 2017 at 11:22:12AM +0800, Figo.zhang wrote:
[...]
> > Heterogeneous Memory Management (HMM) (description and justification)
> >
> > Today device driver expose dedicated memory allocation API through their
> > device file, often relying on a combination of IOCTL and mmap calls.
On Wed, Apr 05 2017, Matthew Wilcox wrote:
> On Thu, Apr 06, 2017 at 10:02:48AM +1000, NeilBrown wrote:
>> If you are concerned about space in 'struct address_space', just prune
>> some wastage.
>
> I'm trying to (via wlists). still buggy though.
Cool.
(I wonder what a wlist is weighted
On Thu, 2017-04-06 at 04:58 +, Song, Hongyan wrote:
> Hi Srinivas,
> I have checked the patch dose not meets my requirement for ISH.
> With this patch sensor properties still losing after resume from S3.
What is your test case? I want to try.
Thanks,
Srinivas
>
> BR
> Song Hongyan
>
Hi Bjorn,
On Wednesday 05 April 2017 10:22 PM, Bjorn Helgaas wrote:
> On Wed, Apr 05, 2017 at 02:22:21PM +0530, Kishon Vijay Abraham I wrote:
>> Introduce a new EP core layer in order to support endpoint functions in
>> linux kernel. This comprises the EPC library (Endpoint Controller Library)
>>
On Wed, Apr 05, 2017 at 06:43:03AM -0700, David Miller wrote:
> This patch does too many things at one time. Each entry in that list
> of changes above should be a separate change, all posted together as
> a group as a proper patch series.
And please start a new thread with the next posting.
Note that the nvme completion queues are still on the host memory, so
this means we have lost the ordering between data and completions as
they go to different pcie targets.
Hmm, in this simple up/down case with a switch, I think it might
actually be OK.
Transactions might not complete at
From: Huang Ying
This patchset is to optimize the performance of Transparent Huge Page
(THP) swap.
Hi, Andrew, could you help me to check whether the overall design is
reasonable?
Hi, Hugh, Shaohua, Minchan and Rik, could you help me to review the
swap part of the patchset?
Hi, Andrea could
From: Huang Ying
In the original THP swapping out implementation, before splitting the
THP (Transparent Huage Page), the swap cluster will be allocated and
the THP will be added into the swap cache. But it is possible that
the THP cannot be split, and we must delete the THP from the swap
cache
From: Huang Ying
In this patch, splitting huge page is delayed from almost the first
step of swapping out to after allocating the swap space for the
THP (Transparent Huge Page) and adding the THP into the swap cache.
This will batch the corresponding operation, thus improve THP swap out
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