3.18-stable review patch. If anyone has any objections, please let me know.
--
From: Marcel Hasler
commit bdc3478f90cd4d2928197f36629d5cf93b64dbe9 upstream.
The stk1160 chip needs QUIRK_AUDIO_ALIGN_TRANSFER. This patch resolves
the issue reported on the mailing list
3.18-stable review patch. If anyone has any objections, please let me know.
--
From: Arnd Bergmann
commit 55c4b906aa2aec3fa66310ec03c6842e34a04b2a upstream.
gcc-6 warns about a pointless loop in exynos_drm_subdrv_open:
drivers/gpu/drm/exynos/exynos_drm_core.c: In function
3.18-stable review patch. If anyone has any objections, please let me know.
--
From: Peter Chen
commit a5d906bb261cde5f881a949d3b0fbaa285dcc574 upstream.
This can fix below dump when the lock is accessed at host
mode due to it is not initialized.
[ 46.119638] INFO: trying
3.18-stable review patch. If anyone has any objections, please let me know.
--
From: Eric Dumazet
commit ffb4d6c8508657824bcef68a36b2a0f9d8c09d10 upstream.
If a TCP socket gets a large write queue, an overflow can happen
in a test in __tcp_retransmit_skb() preventing all
3.18-stable review patch. If anyone has any objections, please let me know.
--
From: Eric Dumazet
[ Upstream commit 8ce48623f0cf3d632e32448411feddccb693d351 ]
Baozeng Ding reported following KASAN splat :
BUG: KASAN: use-after-free in
3.18-stable review patch. If anyone has any objections, please let me know.
--
From: WANG Cong
[ Upstream commit 73d2c6678e6c3af7e7a42b1e78cd0211782ade32 ]
Andrey reported a kernel crash:
general protection fault: [#1] SMP KASAN
Dumping ftrace buffer:
(ftrace
3.18-stable review patch. If anyone has any objections, please let me know.
--
From: Linus Torvalds
commit 38f7bd94a97b542de86a2be9229289717e33a7a4 upstream.
This reverts commit c845acb324aa85a39650a14e7696982ceea75dc1.
It turns out that it just replaces one deadlock with
This patchset is the initial patchset for Allwinner DE2 support.
It contains the support of clocks in DE2 and the mixers in DE2.
The SoC used to develop this patchset is V3s, as V3s is the simplest
one of the SoCs that have DE2.
(Allwinner V3s features only one mixer, although its clock control
The "Display Engine 2.0" in Allwinner newer SoCs contains a clock
management unit for its subunits, like the DE CCU in A80.
Add a sunxi-ng style driver for it.
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Fixed the inconsistence between mixer_div clocks' number and real clock.
Changes in
As we are going to add support for the Allwinner DE2 Mixer in sun4i-drm
driver, we will finally have two types of layers.
Each layer is bound to a drm_plane that is CRTC-specific, so we create
them when initializing CRTC (calling sun4i_layers_init, which will be
generalized in next patch). The
Allwinner V3s SoC have a display engine which have a different pipeline
with older SoCs.
Add document for it (new compatibles and the new "mixer" part).
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Removed the refactor at TCON chapter.
Changes in v3:
- Remove the description of having a
Allwinner "Display Engine 2.0" contains some clock controls in it.
In order to add them as clock drivers, we need a device tree binding.
Add the binding here.
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Dropped the leading 0 in clock@100 .
Changes in v3:
- Fill the address space
As we are going to add support for the Allwinner DE2 engine in sun4i-drm
driver, we will finally have two types of display engines -- the DE1
backend and the DE2 mixer. They both do some display blending and feed
graphics data to TCON, so I choose to call them both "engine" here.
Abstract the
Allwinner have a new "Display Engine 2.0" in their new SoCs, which comes
with mixers to do graphic processing and feed data to TCON, like the old
backends and frontends.
Add support for the mixer on Allwinner V3s SoC; it's the simplest one.
Currently a lot of functions are still missing -- more
Allwinner V3s features the new "Display Engine 2.0", which can now also
be driven with our subdrivers in sun4i-drm.
Add the compatible string for in sun4i_drv.c, in order to make the
display engine and its components probed.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun4i_drv.c |
Allwinner V3s SoC features a TCON without channel 1.
Add support for it.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 3 ++-
drivers/gpu/drm/sun4i/sun4i_tcon.c | 5 +
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
Allwinner V3s SoC features a set of pins that have functionality of RGB
LCD, the pins are at different pin ban than other SoCs.
Add pinctrl node for them.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git
Allwinner V3s SoC features a "Display Engine 2.0" with only one TCON
which have RGB LCD output.
Add device nodes for it as well as the TCON.
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Dropped leading 0's in unit name.
Changes in v3:
- Change the size of de2_clocks regs according to the
A 480x272 QiaoDian QD43003C0-40-7LED panel is available from Lichee Pi.
This commit connects this panel to Lichee Pi Zero.
Lichee Pi also provides a 800x480 panel without accurate model number,
so do not merge this patch. It will finally come as device tree overlay.
Signed-off-by: Icenowy Zheng
Hi Dmitry,
Em Sat, 15 Apr 2017 22:11:44 -0700
Dmitry Torokhov escreveu:
> Split input documentation into several groups: kernel- and user-facing, and
> notes about individual device drivers. Move device drivers docs into a
> separate subdirectory.
I reviewed and tested Sphinx generation for
Em Sun, 16 Apr 2017 11:08:13 -0300
Mauro Carvalho Chehab escreveu:
> Hi Dmitry,
>
> Em Sat, 15 Apr 2017 22:11:44 -0700
> Dmitry Torokhov escreveu:
>
> > Split input documentation into several groups: kernel- and user-facing, and
> > notes about individual device drivers. Move device drivers
On 04/14/2017 07:27 PM, Sergei Shtylyov wrote:
> On 04/14/2017 07:44 PM, Matthias Schiffer wrote:
>
>> * Multicast addresses are never valid as local address
>> * Link-local IPv6 unicast addresses may only be used as remote when the
>> local address is link-local as well
>> * Don't allow
On 04/14/2017 07:36 PM, Stephen Hemminger wrote:
> On Fri, 14 Apr 2017 18:44:44 +0200
> Matthias Schiffer wrote:
>
>> diff --git a/drivers/net/vxlan.c b/drivers/net/vxlan.c
>> index 07f89b037681..95a71546e8f2 100644
>> --- a/drivers/net/vxlan.c
>> +++ b/drivers/net/vxlan.c
>> @@ -2881,11
On 04/14/2017 07:38 PM, Stephen Hemminger wrote:
> On Fri, 14 Apr 2017 18:44:46 +0200
> Matthias Schiffer wrote:
>
>> As link-local addresses are only valid for a single interface, we can allow
>> to use the same VNI for multiple independent VXLANs, as long as the used
>> interfaces are
Depending on what is being done, the intel_pstate_tracer.py script
needs to be run as root, or can be run as a regular user.
If run the first time as root the results directory will be
incorrect for any subsequent run as a regular user. For any run
as root the specific testname subdirectory will
On Fri, Apr 14, 2017 at 04:27:38PM -0700, Andrei Vagin wrote:
> Hello,
>
> One of our CRIU tests hangs with this patch.
>
> Steps to reproduce:
> curl -o cgroupns.c
>
Hi Michael,
On Sat, Apr 15, 2017 at 07:00:29PM -0700, Michael Scott wrote:
> On Apr 15, 2017 3:18 PM, "Sebastian Reichel" wrote:
>> Droid 4 has wl1835 connected to the OMAP's UART4 port, which is
>
> Technically, I believe the Droid 4 has WL1283 WLAN chip.
>
> - Mike
iFixit [0] has a nice
Hello, Linus.
Unfortunately, the commit to fix the cgroup mount race in the previous
pull request can lead to hangs. The original bug has been around for
a while and isn't too likely to be triggered in usual use cases.
Revert the commit for now.
Thanks.
The following changes since commit
On Sat, Apr 15, 2017 at 10:36 PM, Logan Gunthorpe wrote:
>
>
> On 15/04/17 04:17 PM, Benjamin Herrenschmidt wrote:
>> You can't. If the iommu is on, everything is remapped. Or do you mean
>> to have dma_map_* not do a remapping ?
>
> Well, yes, you'd have to change the code so that iomem pages do
A micro optimization to bypass the free vector checking if the current
CPU has no irq to migrate, also breaks the for_each_online_cpu() loop
when the count reaches the required vectors.
Suggested-by: Thomas Gleixner
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: "H. Peter Anvin"
Cc: Prarit Bhargava
On Sat, Apr 15, 2017 at 8:01 PM, Benjamin Herrenschmidt
wrote:
> On Sat, 2017-04-15 at 15:09 -0700, Dan Williams wrote:
>> I'm wondering, since this is limited to support behind a single
>> switch, if you could have a software-iommu hanging off that switch
>> device object that knows how to catch
On 04/16/2017 05:23 AM, rupert THURNER wrote:
On Sat, Apr 15, 2017 at 10:40 PM, Larry Finger
wrote:
On 04/14/2017 03:26 PM, rupert THURNER wrote:
On Thu, Feb 9, 2017 at 9:09 PM, Larry Finger
wrote:
On 02/09/2017 01:43 PM, Bjorn Helgaas wrote:
[+cc rtl8192ce folks in case they've seen
On 04/15/2017 10:11 PM, Andrea Adami wrote:
> The Sharp SL Series (Zaurus) PXA handhelds have 16/64/128M of NAND flash
> and share the same layout of the first 7M partition, managed by Sharp FTL.
>
> The purpose of this self-contained patch is to add a common parser and
> remove the hardcoded
Hi All
As part of my testing of IO polling [1] I am seeing a NULL pointer dereference
oops that seems to have been introduced in the preparation for 4.11. The kernel
oops output is below and this seems to be due to blk_mq_tag_to_rq returning
NULL in blk_mq_poll in blk-mq.c. I have not had a
that's useful for the scheduler, power management unless
the driver needs to delay in atomic context
look at documentation/timers/timers-howto
Signed-off-by: Karim Eshapa
---
drivers/watchdog/aspeed_wdt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 16/04/17 09:53 AM, Dan Williams wrote:
> ZONE_DEVICE allows you to redirect via get_dev_pagemap() to retrieve
> context about the physical address in question. I'm thinking you can
> hang bus address translation data off of that structure. This seems
> vaguely similar to what HMM is doing.
On 16/04/17 09:44 AM, Dan Williams wrote:
> I think we very much want the dma mapping layer to be in the way.
> It's the only sane semantic we have to communicate this translation.
Yes, I wasn't proposing bypassing that layer, per say. I just meant that
the layer would, in the end, have to
On 4/16/17, 8:03 AM, Matthias Schiffer wrote:
> On 04/14/2017 07:36 PM, Stephen Hemminger wrote:
>> On Fri, 14 Apr 2017 18:44:44 +0200
>> Matthias Schiffer wrote:
>>
>>> diff --git a/drivers/net/vxlan.c b/drivers/net/vxlan.c
>>> index 07f89b037681..95a71546e8f2 100644
>>> ---
Le 13/04/2017 à 10:24, Cyrille Pitchen a écrit :
> Hi Guochun,
>
> Le 13/04/2017 à 04:40, Guochun Mao a écrit :
>> Hi Cyrille,
>>
>> On Wed, 2017-04-12 at 22:57 +0200, Cyrille Pitchen wrote:
>>> Hi Guochun,
>>>
>>> Le 05/04/2017 à 10:37, Guochun Mao a écrit :
When nor's size larger than
Hi all,
Rob, is this version ok for you? If so, I can take it into the
github/spi-nor tree.
Best regards,
Cyrille
Le 13/04/2017 à 19:15, Ludovic Barre a écrit :
> From: Ludovic Barre
>
> This patch adds documentation of device tree bindings for the STM32
> QSPI controller.
>
>
Hi all,
Le 14/04/2017 à 18:15, Marek Vasut a écrit :
> On 04/13/2017 07:15 PM, Ludovic Barre wrote:
>> From: Ludovic Barre
>>
>> The quadspi is a specialized communication interface targeting single,
>> dual or quad SPI Flash memories.
>>
>> It can operate in any of the following modes:
>>
Add driver for the regulator block in the ROHM BD9571MWV-W MFD PMIC.
This block supports three voltage monitors, VD18, VD25, VD33 for the
1V8, 2V5, 3V3 voltage rails and a single voltage regulator for the
DVFS rail.
Signed-off-by: Marek Vasut
Cc: linux-kernel@vger.kernel.org
Cc: Liam Girdwood
Add the MFD part of the ROHM BD9571MWV-M PMIC driver and MAINTAINERS
entry. The MFD part only specifies the regmap bits for the PMIC and
binds the subdevs together.
Signed-off-by: Marek Vasut
Cc: linux-kernel@vger.kernel.org
Cc: Geert Uytterhoeven
Cc: Lee Jones
---
MAINTAINERS
On Sun, Apr 16, 2017 at 6:02 PM, Larry Finger wrote:
> On 04/16/2017 05:23 AM, rupert THURNER wrote:
>>
>> On Sat, Apr 15, 2017 at 10:40 PM, Larry Finger
>> wrote:
>>>
>>> On 04/14/2017 03:26 PM, rupert THURNER wrote:
On Thu, Feb 9, 2017 at 9:09 PM, Larry Finger
wrote:
>
Hi Sebastian,
> Avoid NULL pointer dereference occurring due to freeing
> skb containing an error pointer. It can easily be triggered
> by using the driver with broken uart (i.e. due to misconfigured
> pinmuxing).
>
> Fixes: 371805522f87 ("bluetooth: hci_uart: add LL protocol serdev driver
>
Hi Linus,
The following changes since commit 0fa974b8b6106e053595e5481ef6fdbf5c60b457:
Merge tag 'arm-soc/for-4.11/devicetree-arm64-fixes' of
http://github.com/Broadcom/stblinux into fixes (2017-03-24 17:51:50 +0100)
are available in the git repository at:
Dear Greg,
On 2017-04-15 22:50, Greg KH wrote:
On Sat, Apr 15, 2017 at 06:26:22PM +0300, Jarkko Sakkinen wrote:
From: "Maciej S. Szmigiero"
Since commit 1107d065fdf1 ("tpm_tis: Introduce intermediate layer for
TPM access") Atmel 3203 TPM on ThinkPad X61S (TPM firmware version
13.9)
no
Hello Heikki,
I'm working with the new typec class code and have run into a problem.
The struct typec_capability defines a callback function as:
int (*activate_mode)(const struct typec_capability *, int mode, int activate);
From the capability I can get to the corresponding port/plug/partner
On 04/16/2017 01:09 PM, rupert THURNER wrote:
On Sun, Apr 16, 2017 at 6:02 PM, Larry Finger wrote:
On 04/16/2017 05:23 AM, rupert THURNER wrote:
On Sat, Apr 15, 2017 at 10:40 PM, Larry Finger
wrote:
On 04/14/2017 03:26 PM, rupert THURNER wrote:
On Thu, Feb 9, 2017 at 9:09 PM, Larry
On Sun, Apr 09, 2017 at 09:41:31AM +0800, Geliang Tang wrote:
> Use setup_timer() instead of init_timer() to simplify the code.
>
> Signed-off-by: Geliang Tang
Applied to for-next, thanks!
signature.asc
Description: PGP signature
Was there a conclusion to this discussion? I didn't see anything
definitive in the thread...
Notes below...
On Fri, Dec 16, 2016 at 3:14 AM, Arnd Bergmann wrote:
> [Fixed linux-arm-kernel mailing list address, sorry for the duplicate,
> I'm not reposting all the ugly patches though, unless
On 04/16/2017 09:33 AM, Karim Eshapa wrote:
that's useful for the scheduler, power management unless
the driver needs to delay in atomic context
look at documentation/timers/timers-howto
Signed-off-by: Karim Eshapa
---
drivers/watchdog/aspeed_wdt.c | 2 +-
1 file changed, 1 insertion(+), 1
Hi Thomas,
this pull request contains new material for the 4.12. Please note there is a
shared branch with ARM64, arch-timer-errata, which provides the necessary
changes for the errata handling: https://lkml.org/lkml/2017/4/7/369
- Provide a framework to handle errata gracefuly for
You all know the drill by now. We're in the late rc phase, and this
may be the last rc if nothing surprising happens.
Things have been pretty calm this past week (the beginning of the week
seemed particularly calm, and then as usual Friday happened..). We
have a number of reverts for things that
From: Marc Zyngier
Should we ever have a workaround for an erratum that is detected using
a capability and affecting a particular CPU, it'd be nice to have
a way to probe them directly.
Acked-by: Thomas Gleixner
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/arch_timer.h | 1 +
From: Marc Zyngier
We're currently stuck with DT when it comes to handling errata, which
is pretty restrictive. In order to make things more flexible, let's
introduce an infrastructure that could support alternative discovery
methods. No change in functionality.
Acked-by: Thomas Gleixner
From: Marc Zyngier
this_cpu_has_cap() only checks the feature array, and not the errata
one. In order to be able to check for a CPU-local erratum, allow it
to inspect the latter as well.
This is consistent with cpus_have_cap()'s behaviour, which includes
errata already.
Acked-by: Thomas
From: Marc Zyngier
As we're about to allow per CPU cntkctl_el1 configuration, we cannot
rely on the register value to be common when performing power
management.
Let's turn saved_cntkctl into a per-cpu variable.
Acked-by: Thomas Gleixner
Signed-off-by: Marc Zyngier
---
From: Marc Zyngier
Some minor erratum may not be fixed in further revisions of a core,
leading to a situation where the workaround needs to be updated each
time an updated core is released.
Introduce a MIDR_ALL_VERSIONS match helper that will work for all
versions of that MIDR, once and for
From: Marc Zyngier
Cortex-A73 (all versions) counter read can return a wrong value
when the counter crosses a 32bit boundary.
The workaround involves performing the read twice, and to return
one or the other depending on whether a transition has taken place.
Acked-by: Thomas Gleixner
From: Alexander Kochetkov
The clock supplying the arm-global-timer on the rk3188 is coming from the
the cpu clock itself and thus changes its rate everytime cpufreq adjusts
the cpu frequency making this timer unsuitable as a stable clocksource
and sched clock.
The rk3188, rk3288 and following
From: Linus Walleij
It turns out that the Cortina Gemini timer block is just a
standard IP block from Faraday Technology named FTTMR010.
In order to make things clear and understandable, we rename the
bindings with a Faraday compatible as primary and the Cortina
gemini as a more specific case.
From: Linus Walleij
The plain Faraday FTTMR010 timer needs a clock to figure out its
tick rate, and the gemini reads it directly from the system
controller set-up. Split the init function and add two paths for
the two compatible-strings. We only support clocking using PCLK
because of lack of
From: Linus Walleij
After some research it turns out that the "Gemini" timer is
actually a generic IP block from Faraday Technology named
FTTMR010, so as to not make things too confusing we need to
rename the driver and its symbols to make sense.
The implementation remains the same in this
From: Alexander Kochetkov
Make all properties description in form '"rockchip,-timer",
"rockchip,rk3288-timer"' for all chips found in linux kernel.
Suggested-by: Heiko Stübner
Signed-off-by: Alexander Kochetkov
Acked-by: Rob Herring
Reviewed-by: Heiko Stuebner
Signed-off-by: Daniel Lezcano
From: Alexander Kochetkov
The clocksource and the sched_clock provided by the arm_global_timer
are quite unstable because their rates depend on the cpu frequency.
On the other side, the arm_global_timer has a higher rating than the
rockchip_timer, it will be selected by default by the time
From: Alexander Kochetkov
The patch add two timers to all rk3188 based boards.
The first timer is from alive subsystem and it act as a backup
for the local timers at sleep time. It act the same as other
SoC rockchip timers already present in kernel.
The second timer is from CPU subsystem and
From: Rafał Miłecki
Printing with pr_* functions requires adding line break manually.
Signed-off-by: Rafał Miłecki
Acked-by: Thierry Reding
Signed-off-by: Daniel Lezcano
---
drivers/clocksource/arc_timer.c | 14 +++---
drivers/clocksource/arm_arch_timer.c | 2 +-
From: Marc Zyngier
In order to access clocksource_counter from the errata handling code,
move it (together with the related structures and functions) towards
the top of the file.
Acked-by: Thomas Gleixner
Signed-off-by: Marc Zyngier
---
drivers/clocksource/arm_arch_timer.c | 62
From: Marc Zyngier
In order to deal with ACPI enabled platforms suffering from the
HISILICON_ERRATUM_161010101, let's add the required OEM data that
allow the workaround to be enabled.
Acked-by: Thomas Gleixner
Tested-by: dann frazier
Tested-by: Hanjun Guo
Reviewed-by: Hanjun Guo
From: Alexander Kochetkov
Property set to '"rockchip,rk3228-timer", "rockchip,rk3288-timer"'
to match devicetree bindings.
Signed-off-by: Alexander Kochetkov
Suggested-by: Heiko Stübner
Reviewed-by: Heiko Stuebner
Signed-off-by: Daniel Lezcano
---
arch/arm/boot/dts/rk322x.dtsi | 2 +-
1
From: Russell King
Rather than reading the clock rate three times, read it once - we are
about to add a fourth usage.
Signed-off-by: Russell King
Signed-off-by: Daniel Lezcano
---
drivers/clocksource/time-orion.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git
From: Russell King
Add an implementation for the ARM delay timer, which is used for
udelay(). This provides less CPU dependent and more accurate delays -
the CPU loop on Marvell Dove appears to calibrate to around 6% too
short.
Signed-off-by: Russell King
Signed-off-by: Daniel Lezcano
---
From: Marc Zyngier
Not all errata need to workaround all access types. Allow them to
be optional.
Acked-by: Thomas Gleixner
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/arch_timer.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
From: Marc Zyngier
Just as we're able to identify a broken platform using some DT
information, let's enable a way to spot the offenders with ACPI.
The difference is that we can only match on some OEM info instead
of implementation-specific properties. So in order to avoid the
insane
From: Marc Zyngier
Userspace being allowed to use read CNTVCT_EL0 anytime (and not
only in the VDSO), we need to enable trapping whenever a cntvct
workaround is enabled on a given CPU.
Acked-by: Thomas Gleixner
Signed-off-by: Marc Zyngier
---
drivers/clocksource/arm_arch_timer.c | 45
From: Marc Zyngier
Instead of applying a CPU-specific workaround to all CPUs in the system,
allow it to only affect a subset of them (typical big-little case).
This is done by turning the erratum pointer into a per-CPU variable.
Acked-by: Thomas Gleixner
Signed-off-by: Marc Zyngier
---
From: Marc Zyngier
In order to work around Cortex-A73 erratum 858921 in a subsequent
patch, add the required capability that advertise the erratum.
As the configuration option it depends on is not present yet,
this has no immediate effect.
Acked-by: Thomas Gleixner
Acked-by: Daniel Lezcano
From: Marc Zyngier
The way we work around errata affecting set_next_event is not very
nice, at it imposes this workaround on errata that do not need it.
Add new workaround hooks and let the existing workarounds use them.
Acked-by: Thomas Gleixner
Signed-off-by: Marc Zyngier
---
From: Marc Zyngier
As we're about to move things around, let's start with the low
level read/write functions. This allows us to use these functions
in the errata handling code without having to use forward declaration
of static functions.
Acked-by: Thomas Gleixner
Acked-by: Mark Rutland
From: Marc Zyngier
Let's move the handling of workarounds affecting set_next_event
to the affected function, instead of overriding the pointers
as an afterthough. Yes, this is an extra indirection on the
erratum handling path, but the HW is busted anyway.
This will allow for some more
From: Marc Zyngier
As we're about to introduce a new workaround that is specific to
Cortex-A73, let's define the coresponding MIDR.
Acked-by: Thomas Gleixner
Acked-by: Mark Rutland
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff
From: Marc Zyngier
Since people seem to make a point in breaking the userspace visible
counter, we have no choice but to trap the access. Add the required
handler.
Acked-by: Thomas Gleixner
Acked-by: Mark Rutland
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/esr.h | 2 ++
On 04/15/2017 12:55 PM, Matias Bjørling wrote:
> Hi Jens,
>
> With this merge window, we like to push pblk upstream. It is a new
> host-side translation layer that implements support for exposing
> Open-Channel SSDs as block devices.
>
> We have described pblk in the LightNVM paper "LightNVM:
On Fri, 14 Apr, at 08:05:07PM, Thomas Gleixner wrote:
> On Wed, 5 Apr 2017, David Howells wrote:
>
> > From: Kyle McMartin
> >
> > Make sysrq+x exit secure boot mode on x86_64, thereby allowing the running
> > kernel image to be modified. This lifts the lockdown.
> >
> > Signed-off-by: Kyle
On Thu, 13 Apr 2017, Josh Poimboeuf wrote:
> Add missing newlines to some pr_err() strings.
>
> Signed-off-by: Josh Poimboeuf
> Acked-by: Miroslav Benes
> Acked-by: Jessica Yu
Applied to for-4.12/upstream. Thanks,
--
Jiri Kosina
SUSE Labs
Hi Paul,
On Sun, Apr 16, 2017 at 12:35 PM, Paul Kocialkowski wrote:
> The move to a dedicated pwm_backlight_initial_power_state function in
> commit 7613c922315e308a6486d802abed2eb74443dffd modified the condition
> to set the enable gpio as output. This breaks specific use cases using
> that
On Wed, Apr 12, 2017 at 08:02:45AM -0700, Stephen Boyd wrote:
> On 04/08, Daniel Lezcano wrote:
> >
> > Example:
> > pmic: pmic@f800 {
> > @@ -24,4 +29,5 @@ Example:
> > interrupt-controller;
> > #interrupt-cells = <2>;
> > pmic-gpios = < 2
On Tue, Apr 11, 2017 at 09:28:55PM +0800, icen...@aosc.io wrote:
> 在 2017-04-11 17:13，Maxime Ripard 写道：
> > On Sun, Apr 09, 2017 at 02:50:24AM +0800, Icenowy Zheng wrote:
> > > The CPU on Allwinner H3 can do dynamic frequency scaling.
> > >
> > > Add a DVFS table based on the one tweaked by
在 2017-04-17 04:57，Maxime Ripard 写道：
On Tue, Apr 11, 2017 at 09:28:55PM +0800, icen...@aosc.io wrote:
在 2017-04-11 17:13，Maxime Ripard 写道：
> On Sun, Apr 09, 2017 at 02:50:24AM +0800, Icenowy Zheng wrote:
> > The CPU on Allwinner H3 can do dynamic frequency scaling.
> >
> > Add a DVFS table
On 04/16/2017 01:02 AM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 4.4.62 release.
There are 18 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be
On 04/16/2017 01:03 AM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 4.9.23 release.
There are 31 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be
On 04/16/2017 01:04 AM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 4.10.11 release.
There are 29 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be
Before this patch, m25p80_read() supported few SPI protocols:
- regular SPI 1-1-1
- SPI Dual Output 1-1-2
- SPI Quad Output 1-1-4
On the other hand, m25p80_write() only supported SPI 1-1-1.
This patch updates both m25p80_read() and m25p80_write() functions to let
them support SPI 1-2-2 and SPI
This patch changes the prototype of spi_nor_scan(): its 3rd parameter
is replaced by a 'struct spi_nor_hwcaps' pointer, which tells the spi-nor
framework about the actual hardware capabilities supported by the SPI
controller and its driver.
Besides, this patch also introduces a new 'struct
Signed-off-by: Cyrille Pitchen
---
drivers/mtd/spi-nor/spi-nor.c | 19 ---
include/linux/mtd/spi-nor.h | 2 ++
2 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 3bb2adff306b..2377fe54f8b9 100644
This patch extracts some chunks from spi_nor_scan() and moves them into
a new spi_nor_init() function.
Indeed, spi_nor_init() regroups all the required SPI flash commands to be
sent to the SPI flash memory before performing any runtime operations
(Fast Read, Page Program, Sector Erase, ...).
Each slab kmem cache has per cpu array caches. The array caches are
created when the kmem_cache is created, either via kmem_cache_create()
or lazily when the first object is allocated in context of a kmem
enabled memcg. Array caches are replaced by writing to /proc/slabinfo.
Array caches are
Hi all,
based on git-hub/spi-nor.
The 4 patches have passed the checkpatch test.
DISCLAIMER: despite what the subjet claims, I've removed the SFDP patches from
this
version since they are still RFC/WIP. However I've chosen not to change the
subjet
line so it's easier to make the link between
于 2017年4月17日 GMT+08:00 上午4:57:40, Maxime Ripard
写到:
>On Tue, Apr 11, 2017 at 09:28:55PM +0800, icen...@aosc.io wrote:
>> 在 2017-04-11 17:13，Maxime Ripard 写道：
>> > On Sun, Apr 09, 2017 at 02:50:24AM +0800, Icenowy Zheng wrote:
>> > > The CPU on Allwinner H3 can do dynamic frequency scaling.
>>
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