[PATCH 1/2] MIPS: ralink: Fix build error due to missing header

Previously, was included before ralink_regs.h in all ralink files - leading to being implicitly included. After commit 26dd3e4ff9ac ("MIPS: Audit and remove any unnecessary uses of module.h") removed the inclusion of module.h from multiple places, some ralink platforms failed to build with the

Re: [PATCH v2] xattr: Enable security.capability in user namespaces

Stefan Berger writes: > On 07/18/2017 03:01 AM, James Morris wrote: >> On Thu, 13 Jul 2017, Stefan Berger wrote: >> >>> A file shared by 2 containers, one mapping root to uid=1000, the other >>> mapping >>> root to uid=2000, will show these two xattrs on the host

Re: [PATCH] Staging: pi433: Coding style fixes

On Tue, Jul 18, 2017 at 02:41:33PM +0200, Simo Koskinen wrote: > Fixes if-statement related warning and errors reported > by checkpatch.pl > > Signed-off-by: Simo Koskinen > --- > drivers/staging/pi433/pi433_if.c | 253 > +-- >

Re: [PATCH v2] xattr: Enable security.capability in user namespaces

Vivek Goyal writes: > On Tue, Jul 18, 2017 at 08:30:09AM -0400, Vivek Goyal wrote: >> On Tue, Jul 18, 2017 at 08:05:18AM -0400, Stefan Berger wrote: >> > On 07/18/2017 07:48 AM, Vivek Goyal wrote: >> > > On Mon, Jul 17, 2017 at 04:50:22PM -0400, Stefan Berger wrote: >> > > >

[PATCH] arc: Hardcode ARCH_DMA_MINALIGN to max line length we may have

Current implementation relies on L1 line length which might easily be smaller than L2 line (which is usually the case BTW). Imagine this typical case: L2 line is 128 bytes while L1 line is 64-bytes. Now we want to allocate small buffer and later use it for DMA (consider IOC is not available).

commit 16ecba59 breaks 82574L under heavy load.

Commit 16ecba59bc333d6282ee057fb02339f77a880beb has apparently broken at least the 82574L under heavy load (as in load heavy enough to cause packet drops). In this case, when running in MSI-X mode, the Other Causes interrupt fires about 3000 times per second, but not due to link state changes.

Re: [PATCH v2 12/22] fpga: intel: fme: add header sub feature support

On Mon, Jul 17, 2017 at 8:17 PM, Wu, Hao wrote: >> On Sun, Jun 25, 2017 at 8:52 PM, Wu Hao wrote: >> >> Hi Hao, >> >> I'm making my way through this (very large) patchset. Some minor >> comments below. >> > > Hi Alan > > Thanks for your review. : ) Hi Hao,

Re: [PATCH] efifb: allow user to disable write combined mapping.

On Tue, Jul 18, 2017 at 04:09:09PM +1000, Dave Airlie wrote: > This patch allows the user to disable write combined mapping > of the efifb framebuffer console using an nowc option. > > A customer noticed major slowdowns while logging to the console > with write combining enabled, on other tasks

Re: [PATCH v10 2/3] arm/syscalls: Check address limit on user-mode return

On Wed, 2017-06-14 at 18:12 -0700, Thomas Garnier wrote: > Ensure the address limit is a user-mode segment before returning to > user-mode. Otherwise a process can corrupt kernel-mode memory and > elevate privileges [1]. > > The set_fs function sets the TIF_SETFS flag to force a slow path on >

Re: [PATCH v2 8/8] staging: fsl-mc: allow the driver compile multi-arch

Hi Arnd, On 07/18/2017 05:25 PM, Arnd Bergmann wrote: > On Tue, Jul 18, 2017 at 3:37 PM, wrote: > >> --- a/drivers/staging/fsl-dpaa2/Kconfig >> +++ b/drivers/staging/fsl-dpaa2/Kconfig >> @@ -4,7 +4,7 @@ >> >> config FSL_DPAA2 >> bool "Freescale DPAA2 devices"

Re: [PATCH v2 8/8] staging: fsl-mc: allow the driver compile multi-arch

On Tue, Jul 18, 2017 at 4:36 PM, Laurentiu Tudor wrote: > Good point, I'll take care of it. But don't you mean COMPILE_TEST be > added on the actual MC_BUS config, like so: > > config FSL_MC_BUS > bool "QorIQ DPAA2 fsl-mc bus driver" > - depends on OF &&

Re: [PATCH 3/3] ghes_edac: add platform check to enable ghes_edac

On 7/17/2017 3:59 PM, Toshi Kani wrote: The ghes_edac driver was introduced in 2013 [1], but it has not been enabled by any distro yet. Ubuntu is expected to enable this soon. -- Jeffrey Hugo Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc. Qualcomm

[PATCH] pid: kill pidhash_size in pidhash_init

After commit 3d375d78593c ("mm: update callers to use HASH_ZERO flag"), drop unused pidhash_size in pidhash_init(). Signed-off-by: Kefeng Wang --- kernel/pid.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/kernel/pid.c b/kernel/pid.c index 731c4e5..c69c30d

Re: [PATCH] sctp: fully initialize the IPv6 address in sctp_v6_to_addr()

On Tue, Jul 18, 2017 at 4:55 PM, Alexander Potapenko wrote: > KMSAN reported use of uninitialized sctp_addr->v4.sin_addr.s_addr and > sctp_addr->v6.sin6_scope_id in sctp_v6_cmp_addr() (see below). > Make sure all fields of an IPv6 address are initialized, which > guarantees

[PATCH v3 2/5] ACPI / boot: Correct address space of __acpi_map_table()

Sparse complains about wrong address space used in __acpi_map_table() and in __acpi_unmap_table(). arch/x86/kernel/acpi/boot.c:127:29: warning: incorrect type in return expression (different address spaces) arch/x86/kernel/acpi/boot.c:127:29:expected char *

[PATCH v3 1/5] ACPI / boot: Don't define unused variables

Some code in acpi_parse_x2apic() conditionally compiled, though parts of it are being used in any case. This annoys gcc. arch/x86/kernel/acpi/boot.c: In function ‘acpi_parse_x2apic’: arch/x86/kernel/acpi/boot.c:203:5: warning: variable ‘enabled’ set but not used [-Wunused-but-set-variable] u8

[PATCH v3 3/5] ACPI / boot: Add number of legacy IRQs to debug output

Sometimes it's useful to have when mp_config_acpi_legacy_irqs() is called. Signed-off-by: Andy Shevchenko --- arch/x86/kernel/acpi/boot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/acpi/boot.c

[PATCH v3 4/5] ACPI / boot: Not all platform require acpi_reduced_hw_init()

Some platform might take care of legacy devices on theirs own. Let's allow them to do that by exporting a weak function. Signed-off-by: Andy Shevchenko --- arch/x86/kernel/acpi/boot.c | 2 +- include/linux/acpi.h| 3 +++ 2 files changed, 4

Re: [PATCH v2] serial: 8250: fix error handling in of_platform_serial_probe()

On Tue, Jul 18, 2017 at 2:32 PM, Alexey Khoroshilov wrote: > clk_disable_unprepare(info->clk) is missed in of_platform_serial_probe(), > while irq_dispose_mapping(port->irq) is missed in of_platform_serial_setup(). > > Found by Linux Driver Verification project

[PATCH] staging: rtl8723bs: rtw_efuse: Fix a misspell

Fix a comment misspell Signed-off-by: Xaralampos Mainas --- drivers/staging/rtl8723bs/core/rtw_efuse.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/rtl8723bs/core/rtw_efuse.c b/drivers/staging/rtl8723bs/core/rtw_efuse.c index

Re: [RFC PATCH v1 00/11] Create fast idle path for short idle periods

On Tue, Jul 18, 2017 at 02:56:47PM +0800, Li, Aubrey wrote: > On 2017/7/18 14:43, Thomas Gleixner wrote: > > On Mon, 17 Jul 2017, Andi Kleen wrote: > > > >>> We need a tradeoff here IMHO. I'll check Daniel's work to understand > >>> how/if > >>> it's better than menu governor. > >> > >> I still

Re: [PATCH v5 4/4]: perf/core: complete replace of lists by rb trees for pinned and flexible groups at perf_event_context

Alexey Budankov writes: >> You probably also want to explain this change, for example change the >> @group_list description, saying that something else links into it now. >> > > The whole patch as a single commit, attached to patch v5 4/4, may provide > the

Re: [PATCH v5 4/4]: perf/core: complete replace of lists by rb trees for pinned and flexible groups at perf_event_context

Hi, On 18.07.2017 18:08, Alexander Shishkin wrote: > Alexey Budankov writes: > >> Ok. I see. So what are the next steps needs to be taken towards the upstream >> of this work? >> What do I need to do more to have this stuff included into the kernel? >> Could

Re: [PATCH] x86: kernel: acpi: fix an invalid argument passing in io_apic.c

Seunghun, On Tue, 18 Jul 2017, Seunghun Han wrote: first of all thanks for the patch and the analysis. > I'm Seunghun Han, and I work for National Security Research Institute of > South Korea. While I appreciate your detailed description of the problem, please try to follow the rules for

Re: [PATCH] arc: Hardcode ARCH_DMA_MINALIGN to max line length we may have

On 07/18/2017 07:31 AM, Alexey Brodkin wrote: Current implementation relies on L1 line length which might easily be smaller than L2 line (which is usually the case BTW). Imagine this typical case: L2 line is 128 bytes while L1 line is 64-bytes. Now we want to allocate small buffer and later use

Re: [PATCH v2 01/22] docs: fpga: add a document for Intel FPGA driver overview

On Tue, Jul 18, 2017 at 12:22 AM, Greg KH wrote: > On Mon, Jul 17, 2017 at 03:14:29PM -0500, Alan Tull wrote: >> > Also, we're thinking that some operations require that you first "acquire >> > ownership" of the respective device, which I believe maps more easily to >> > open()

[PATCH] staging: goldfish: Use __func__ instead of function name

Replace hard-coded function names in strings with "%s", __func__ in the goldfish_nand.c file. Issue found by checkpatch.pl. Signed-off-by: Chris Coffey --- drivers/staging/goldfish/goldfish_nand.c | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-)

Re: [PATCH v2 0/7] staging: fsl-mc: make the driver compile on other architectures

Hi Arnd, On 07/18/2017 05:26 PM, Arnd Bergmann wrote: > On Tue, Jul 18, 2017 at 3:37 PM, wrote: >> From: Laurentiu Tudor >> >> Apart from a small change (first patch) which adds a missing comment, >> this series make the bus driver compile on

Re: [PATCH v2 2/2] livepatch: add shadow variable sample programs

On Wed 2017-06-28 11:37:27, Joe Lawrence wrote: > diff --git a/samples/livepatch/livepatch-shadow-mod.c > b/samples/livepatch/livepatch-shadow-mod.c > new file mode 100644 > index ..423f4b7b0adb > --- /dev/null > +++ b/samples/livepatch/livepatch-shadow-mod.c > + * Usage > + * - >

Re: [PATCH 03/11] clk: sunxi-ng: a83t: Support new timing mode for mmc2 clock

On Mon, Jul 17, 2017 at 06:12:35PM +0800, Chen-Yu Tsai wrote: > On Mon, Jul 17, 2017 at 5:14 PM, Maxime Ripard > wrote: > > Hi, > > > > On Fri, Jul 14, 2017 at 02:42:54PM +0800, Chen-Yu Tsai wrote: > >> The MMC2 clock supports a new timing mode. When the new mode

Re: [PATCH v2] dt-bindings: display: sunxi: Improve endpoint ID scheme readability

On Tue, Jul 18, 2017 at 12:02:01PM +0800, Chen-Yu Tsai wrote: > The explanation for the endpoint ID numbering scheme is convoluted > and hard to understand. > > This patch aims to improve the readability of it by combining the > existing two paragraphs, while also providing a diagram example, >

Re: [PATCH] replace incorrect strscpy use in FORTIFY_SOURCE

On Fri, Jul 14, 2017 at 04:51:31PM -0700, Kees Cook wrote: > On Fri, Jul 14, 2017 at 2:28 PM, Daniel Micay wrote: > > Using strscpy was wrong because FORTIFY_SOURCE is passing the maximum > > possible size of the outermost object, but strscpy defines the count > > parameter

Re: [PATCH v2] xattr: Enable security.capability in user namespaces

On Tue, Jul 18, 2017 at 09:21:22AM -0400, Stefan Berger wrote: > On 07/18/2017 08:30 AM, Vivek Goyal wrote: > > On Tue, Jul 18, 2017 at 08:05:18AM -0400, Stefan Berger wrote: > > > On 07/18/2017 07:48 AM, Vivek Goyal wrote: > > > > On Mon, Jul 17, 2017 at 04:50:22PM -0400, Stefan Berger wrote: > >

[PATCH] sctp: fully initialize the IPv6 address in sctp_v6_to_addr()

KMSAN reported use of uninitialized sctp_addr->v4.sin_addr.s_addr and sctp_addr->v6.sin6_scope_id in sctp_v6_cmp_addr() (see below). Make sure all fields of an IPv6 address are initialized, which guarantees that the IPv4 fields are also initialized.

Re: [PATCH 1/1] mm/slub.c: add a naive detection of double free or corruption

On Mon, 17 Jul 2017, Alexander Popov wrote: > Christopher, if I change BUG_ON() to VM_BUG_ON(), it will be disabled by > default > again, right? It will be enabled if the distro ships with VM debugging on by default.

[PATCH v3 0/5] ACPI / boot: Few amendments

This series does few amendments to architectural ACPI code related to boot, in particularly to arch/x86/kernel/acpi/boot.c. First two patches are amendments to satisfy compiler and static analyzer (the order is changed from first version which had been applied; in case of partial update first

Re: [PATCH] xen/x86: fix cpu hotplug

On 07/05/2017 10:05 AM, Juergen Gross wrote: > Commit dc6416f1d711eb4c1726e845d653235dcaae12e1 ("xen/x86: Call > cpu_startup_entry(CPUHP_AP_ONLINE_IDLE) from xen_play_dead()") > introduced an error leading to a stack overflow of the idle task when > a cpu was brought offline/online many times: by

[PATCH v3 5/5] ACPI / boot: Don't handle SCI on HW reduced platforms

As per note in 5.2.9 Fixed ACPI Description Table (FADT) chapter of ACPI specification OSPM will ignore fields related to the ACPI HW register interface, one of which is SCI_INT. Follow the spec and ignore any configuration done for interrupt line defined by SCI_INT if FADT specifies HW reduced

Re: [PATCH v5 4/4]: perf/core: complete replace of lists by rb trees for pinned and flexible groups at perf_event_context

Alexey Budankov writes: > Ok. I see. So what are the next steps needs to be taken towards the upstream > of this work? > What do I need to do more to have this stuff included into the kernel? > Could you please clarify this? Well, normally you'd be sending new

RE: [PATCH] Coccinelle report script for refcounters

On Tue, 18 Jul 2017, Reshetova, Elena wrote: > > On Tue, 18 Jul 2017, Reshetova, Elena wrote: > > > > > > On Tue, 18 Jul 2017, Elena Reshetova wrote: > > > > > > > > > The below script can be used to detect potential misusage > > > > > of atomic_t type and API for reference counting purposes. >

Re: [PATCH v2 1/2] video/hdmi: Introduce helpers for the HDMI audio infoframe payload

Hi, On Tue, Jul 18, 2017 at 4:20 AM, Chris Zhong wrote: > The DP is using the same audio infoframe payload as hdmi, per DP 1.3 > spec, but it has a different header. Provide a new interface here, > it just packs the payload. > > Signed-off-by: Chris Zhong

Re: [PATCHv2 08/10] x86/mm: Replace compile-time checks for 5-level with runtime-time

On Tue, Jul 18, 2017 at 04:24:06PM +0200, Juergen Gross wrote: > On 18/07/17 16:15, Kirill A. Shutemov wrote: > > diff --git a/arch/x86/xen/mmu_pv.c b/arch/x86/xen/mmu_pv.c > > index cab28cf2cffb..b0530184c637 100644 > > --- a/arch/x86/xen/mmu_pv.c > > +++ b/arch/x86/xen/mmu_pv.c > > @@ -1209,7

parisc:generic-64bit_defconfig build failures due to 'kbuild: handle libs-y archives separately...'

Hi, parisc64 builds, specifically generic-64bit_defconfig, fail to build in mainline as follows. hppa64-linux-ld: hppa64-linux/bin/../lib/gcc/hppa64-linux/4.9.0/libgcc.a(_divdi3.o)(.text+0xec): cannot reach $$divU hppa64-linux/bin/../lib/gcc/hppa64-linux/4.9.0/libgcc.a(_divdi3.o): In function

Re: [RFC PATCH v1 00/11] Create fast idle path for short idle periods

On 7/18/2017 8:20 AM, Paul E. McKenney wrote: 3.2) how to determine if the idle is short or long. My current proposal is to use a tunable value via /sys, while Peter prefers an auto-adjust mechanism. I didn't get the details of an auto-adjust mechanism yet the most obvious way to do this (for

Re: [PATCH v5 4/4]: perf/core: complete replace of lists by rb trees for pinned and flexible groups at perf_event_context

On 18.07.2017 18:23, Alexander Shishkin wrote: > Alexey Budankov writes: > >>> You probably also want to explain this change, for example change the >>> @group_list description, saying that something else links into it now. >>> >> >> The whole patch as a single

Re: [PATCH 3/3] ghes_edac: add platform check to enable ghes_edac

On Tue, 2017-07-18 at 08:39 -0600, Jeffrey Hugo wrote: > On 7/17/2017 3:59 PM, Toshi Kani wrote: > > The ghes_edac driver was introduced in 2013 [1], but it has not > > been enabled by any distro yet.    > > Ubuntu is expected to enable this soon. Interesting. I was told from other distro that

Re: [PATCH 5/6] cgroup: implement cgroup v2 thread support

On 07/17/2017 04:56 PM, Waiman Long wrote: > On 07/17/2017 10:14 AM, Peter Zijlstra wrote: >> On Sun, Jul 16, 2017 at 10:07:20PM -0400, Tejun Heo wrote: >>> v4: - Updated to marking each cgroup threaded as suggested by PeterZ. >>> >>> +On creation, a cgroup is always a domain cgroup and can be

Re: [PATCH] gpio-exar: Use correct property prefix and document bindings

On Mon, Jul 17, 2017 at 1:20 PM, Jan Kiszka wrote: > On 2017-07-17 19:48, Rob Herring wrote: >> On Thu, Jul 13, 2017 at 08:44:26AM +0200, Jan Kiszka wrote: >>> The device-specific property should be prefixed with the vendor name >>> Change this and document the bindings of

Re: [RFC PATCH v12 3/4] Linux Random Number Generator

Am Dienstag, 18. Juli 2017, 10:52:12 CEST schrieb Greg Kroah-Hartman: Hi Greg, > > > I have stated the core concerns I have with random.c in [1]. To remedy > > these core concerns, major changes to random.c are needed. With the past > > experience, I would doubt that I get the changes into

[PATCH] Documentation/devicetree: Update links to PCI DT bindings

Update links to the PDFs of PCI and interrupt mapping bindings, as the previous links are broken. Signed-off-by: Harvey Hunt Cc: Bjorn Helgaas Cc: linux-...@vger.kernel.org Cc: devicet...@vger.kernel.org Cc: linux-kernel@vger.kernel.org ---

Re: [PATCH v2 0/3] pwm: add pwm AO on meson gx

On Fri, Jul 14, 2017 at 01:51:12PM +0800, Jeremy Kerr wrote: > Hi Thierry, > > > I /think/ Jeremy Kerr (To'ed) would be a good person to contact about > > this. > > > > Jeremy, anything you can do about this? > > OK, all sorted. I've updated Jerome's entry in the database to suit. Headers do

Re: [PATCH] powerpc/hugetlb: fix page rights verification in gup_hugepte()

Christophe Leroy writes: > gup_hugepte() checks if pages are present and readable, and > when 'write' is set, also checks if the pages are writable. > > Initially this was done by checking if _PAGE_PRESENT and > _PAGE_READ were set. In addition, _PAGE_WRITE was verified

Re: [PATCH] pid: kill pidhash_size in pidhash_init

Reviewed-by: Pavel Tatashin On 07/18/2017 10:47 AM, Kefeng Wang wrote: After commit 3d375d78593c ("mm: update callers to use HASH_ZERO flag"), drop unused pidhash_size in pidhash_init(). Signed-off-by: Kefeng Wang --- kernel/pid.c | 3

Re: [PATCH v3 1/1] Staging: android/ion: declare function static

On Tue, Jul 18, 2017 at 08:58:22AM +0200, Greg KH wrote: > On Sat, Jul 15, 2017 at 11:43:05AM +, Joseph Wright wrote: > > Declare private function static to fix sparse warning: > > > > ion_cma_heap.c:109:5: warning: symbol '__ion_add_cma_heaps' \ > > was not declared. Should it be static?

Re: [PATCH 1/4] ARM: dts: keystone-k2g: Add PMMC node to support TI-SCI protocol

On 07/17/2017 10:28 PM, Suman Anna wrote: > From: Nishanth Menon > > Texas Instrument's System Control Interface (TI-SCI) Message Protocol > is implemented in Keystone 2 generation 66AK2G SoC with the PMMC entity. > > Add the ti-sci node representing this 66AK2G PMMC module. > >

Re: [PATCH 0/6] Cache coherent device memory (CDM) with HMM v5

On Tue, Jul 18, 2017 at 11:26:51AM +0800, Bob Liu wrote: > On 2017/7/14 5:15, Jérôme Glisse wrote: > > Sorry i made horrible mistake on names in v4, i completly miss- > > understood the suggestion. So here i repost with proper naming. > > This is the only change since v3. Again sorry about the

Re: [PATCH 3/3] ghes_edac: add platform check to enable ghes_edac

On Tue, 2017-07-18 at 10:24 -0600, Jeffrey Hugo wrote: > On 7/18/2017 9:36 AM, Kani, Toshimitsu wrote: > > On Tue, 2017-07-18 at 08:39 -0600, Jeffrey Hugo wrote: > > > On 7/17/2017 3:59 PM, Toshi Kani wrote: > > > > The ghes_edac driver was introduced in 2013 [1], but it has not > > > > been

Re: [PATCH V3 1/2] dmaengine: qcom_hidma: introduce memset support

On Tue, Jul 18, 2017 at 12:26:14PM -0400, Sinan Kaya wrote: > Hi Vinod, > > On 7/18/2017 12:19 PM, Vinod Koul wrote: > > On Thu, Jun 29, 2017 at 10:30:57PM -0400, Sinan Kaya wrote: > > > >> @@ -410,7 +410,40 @@ static int hidma_alloc_chan_resources(struct dma_chan > >> *dmach) > >>

Re: [PATCH 1/3] ACPI / blacklist: add acpi_match_oemlist() interface

On Tue, Jul 18, 2017 at 03:48:54PM +, Kani, Toshimitsu wrote: > This patch defines 'struct acpi_oemlist' in "include/linux/acpi.h" as a I see that. > common structure, and replaces this specific 'struct acpi_blacklist'. And what makes acpi_oemlist "common" and acpi_blacklist "specific"? So

Re: [PATCH 7/7] PCI: dwc: qcom: Add support for IPQ8074 PCIe controller

On Tue 18 Jul 02:58 PDT 2017, Varadarajan Narayanan wrote: > On Mon, Jul 17, 2017 at 03:07:18PM -0700, Bjorn Andersson wrote: > > On Mon 17 Jul 05:04 PDT 2017, Varadarajan Narayanan wrote: [..] > > > > Can you confirm that this is actually version 4 of this block? Or are we > > just incrementing

Re: [RFC PATCH v1 00/11] Create fast idle path for short idle periods

On Tue, Jul 18, 2017 at 02:56:47PM +0800, Li, Aubrey wrote: > 3) for tick nohz idle, we want to skip if the coming idle is short. If we can > skip the tick nohz idle, we then skip all the items depending on it. But, > there > are two hard points: > > 3.1) how to compute the period of the coming

Re: [PATCH resend] Documentation: arm: Replace use of virt_to_phys with __pa_symbol

On 07/17/2017 06:39 AM, Geert Uytterhoeven wrote: > All low-level PM/SMP code using virt_to_phys() should actually use > __pa_symbol() against kernel symbols. Update the documentation to move > away from virt_to_phys(). > > Cfr. commit 6996cbb2372189f7 ("ARM: 8641/1: treewide: Replace uses of >

Re: [PATCH 1/4] gpio: davinci: Use devm_gpiochip_add_data in place of gpiochip_add_data

Hi Keerthy, On 07/18/2017 05:57 AM, Keerthy wrote: > Use the devm version of gpiochip_add_data and pass on the > return value. Reset the static variables to 0 before returning. > > Signed-off-by: Keerthy > --- > drivers/gpio/gpio-davinci.c | 10 -- > 1 file changed, 8

Re: [REGRESSION] 28676d869bbb (scsi: sg: check for valid direction before starting the request) breaks mtx tape library control

> "JT" == Johannes Thumshirn writes: JT> This is fixed with: commit 68c59fcea1f2c6a54c62aa896cc623c1b5bc9b47 Hmm, well, I just pulled and built mainline, which does appear to contain that patch (though it wasn't there when I first started investigating this last week)

Re: [PATCH 2/4] gpio: davinci: Handle the return value of davinci_gpio_irq_setup function

Hi Keerthy, On 07/18/2017 05:57 AM, Keerthy wrote: > Currently davinci_gpio_irq_setup return value is ignored. Handle the > return value appropriately. > > Signed-off-by: Keerthy > --- > drivers/gpio/gpio-davinci.c | 18 +- > 1 file changed, 13 insertions(+),

[PATCH v4 1/5] powerpc: io.h: move iomap.h include so that it can use readq/writeq defs

Subsequent patches in this series makes use of the readq and writeq defines in iomap.h. However, as is, they get missed on the powerpc platform seeing the include comes before the define. This patch moves the include down to fix this. Signed-off-by: Logan Gunthorpe Cc:

[PATCH v4 2/5] iomap: introduce io{read|write}64_{lo_hi|hi_lo}

In order to provide non-atomic functions for io{read|write}64 that will use readq and writeq when appropriate. We define a number of variants of these functions in the generic iomap that will do non-atomic operations on pio but atomic operations on mmio. These functions are only defined if readq

[PATCH v4 3/5] io-64-nonatomic: add io{read|write}64[be]{_lo_hi|_hi_lo} macros

This patch adds generic io{read|write}64[be]{_lo_hi|_hi_lo} macros if they are not already defined by the architecture. (As they are provided by the generic iomap library). The patch also points io{read|write}64[be] to the variant specified by the header name. This is because new drivers are

Re: [RFC][PATCH v2] drm: kirin: Add mode_valid logic to avoid mode clocks we can't generate

On Tue, Jul 18, 2017 at 4:10 AM, Jose Abreu wrote: > Hi John, > > > On 18-07-2017 05:22, John Stultz wrote: >> Currently the hikey dsi logic cannot generate accurate byte >> clocks values for all pixel clock values. Thus if a mode clock >> is selected that cannot match

Re: [PATCH 7/7] signal: Remove kernel interal si_code magic

On Tue, Jul 18, 2017 at 7:06 AM, Eric W. Biederman wrote: > struct siginfo is a union and the kernel since 2.4 has been hiding a union > tag in the high 16bits of si_code using the values: > __SI_KILL > __SI_TIMER > __SI_POLL > __SI_FAULT > __SI_CHLD > __SI_RT > __SI_MESGQ

[PATCH v4 4/5] ntb: ntb_hw_intel: use io-64-nonatomic instead of in-driver hacks

Now that ioread64 and iowrite64 are available in io-64-nonatomic, we can remove the hack at the top of ntb_hw_intel.c and replace it with an include. Signed-off-by: Logan Gunthorpe Cc: Jon Mason Cc: Allen Hubbe Acked-by: Dave Jiang

Re: [PATCH v5 4/4]: perf/core: complete replace of lists by rb trees for pinned and flexible groups at perf_event_context

Alexey Budankov writes: > I see. Do you personally have some more issues that needs to be addressed? > My intention is that this patch v5 4/4 addresses all your comments raised in > the previous reviews. I don't know yet, I haven't started on the actual content

[PATCH v4 5/5] crypto: caam: cleanup CONFIG_64BIT ifdefs when using io{read|write}64

From: Horia Geantă We can now make use of the io-64-nonatomic-lo-hi header to always provide 64 bit IO operations. So this patch cleans up the extra CONFIG_64BIT ifdefs. To be consistent with CAAM engine HW spec: in case of 64-bit registers, irrespective of device

Re: [PATCH 3/7] phy: qcom-qmp: Fix phy pipe clock name

On Tue 18 Jul 01:54 PDT 2017, Varadarajan Narayanan wrote: > On Mon, Jul 17, 2017 at 03:30:47PM -0700, Bjorn Andersson wrote: [..] > > > > This would be the case for any existing dts files, so you're not allowed > > to treat this as an error. > > Since, there are no dts files that presently

[PATCH v4 0/5] make io{read|write}64 globally usable

This is version four of my patchset to enable drivers to use io{read|write}64 on all arches. Changes since v3: - I noticed powerpc didn't use the appropriate functions seeing readq/writeq were not defined when iomap.h was included. Thus I've included a patch to adjust this - Fixed some mistakes

[RFC PATCH v2 03/38] KVM: arm64: Add KVM nesting feature

From: Christoffer Dall Set the initial exception level of the guest to EL2 if nested virtualization feature is enabled. Signed-off-by: Christoffer Dall Signed-off-by: Jintack Lim ---

[RFC PATCH v2 08/38] KVM: arm64: Add EL2 special registers to vcpu context

To support the virtual EL2 execution, we need to maintain the EL2 special registers such as SPSR_EL2, ELR_EL2 and SP_EL2 in vcpu context. Note that SP_EL2 is not accessible in EL2, so we don't need a trap handler for this register. Signed-off-by: Jintack Lim ---

[RFC PATCH v2 14/38] KVM: arm64: Synchronize EL1 system registers on virtual EL2 entry and exit

When running in virtual EL2 we use the shadow EL1 systerm register array for the save/restore process, so that hardware and especially the memory subsystem behaves as code written for EL2 expects while really running in EL1. This works great for EL1 system register accesses that we trap, because

[RFC PATCH v2 05/38] KVM: arm64: Allow userspace to set PSR_MODE_EL2x

From: Christoffer Dall We were not allowing userspace to set a more privileged mode for the VCPU than EL1, but now that we support nesting with a virtual EL2 mode, do allow this! Signed-off-by: Christoffer Dall ---

Re: Regression with suspicious RCU usage splats with cpu_pm change

On Mon, Jul 17, 2017 at 10:41:38PM -0700, Tony Lindgren wrote: > * Paul E. McKenney [170717 05:40]: > > On Sun, Jul 16, 2017 at 11:08:07PM -0700, Tony Lindgren wrote: > > > * Alex Shi [170716 16:25]: > > > > I reused the rcu_irq_enter_irqson()

[RFC PATCH v2 25/38] KVM: arm64: Respect virtual CPTR_EL2.TFP setting

Forward traps due to FP/ASIMD register accesses to the virtual EL2 if virtual CPTR_EL2.TFP is set. Note that if TFP bit is set, then even accesses to FP/ASIMD register from EL2 as well as NS EL0/1 will trap to EL2. So, we don't check the VM's exception level. Signed-off-by: Jintack Lim

[RFC PATCH v2 37/38] KVM: arm64: Respect the virtual HCR_EL2.NV1 bit setting

Forward ELR_EL1, SPSR_EL1 and VBAR_EL1 traps to the virtual EL2 if the virtual HCR_EL2.NV bit is set. This is for recursive nested virtualization. Signed-off-by: Jintack Lim --- arch/arm64/include/asm/kvm_arm.h | 1 + arch/arm64/kvm/sys_regs.c| 18

[RFC PATCH v2 34/38] KVM: arm64: Respect the virtual HCR_EL2.NV bit setting

Forward traps due to HCR_EL2.NV bit to the virtual EL2 if they are not coming from the virtual EL2 and the virtual HCR_EL2.NV bit is set. This is for recursive nested virtualization. Signed-off-by: Jintack Lim --- arch/arm64/include/asm/kvm_arm.h| 1 +

[RFC PATCH v2 29/38] KVM: arm64: Support a VM with VHE considering EL0 of the VHE host

On VHE systems, EL0 of the host kernel is considered as a part of 'VHE host'; The execution of EL0 is affected by system registers set by the VHE kernel including the hypervisor. To emulate this for a VM, we use the same set of system registers (i.e. shadow registers) for the virtual EL2 and EL0

[RFC PATCH v2 38/38] KVM: arm64: Respect the virtual CPTR_EL2.TCPAC setting

Forward CPACR_EL1 traps to the virtual EL2 if virtual CPTR_EL2 is configured to trap CPACR_EL1 accesses from EL1. This is for recursive nested virtualization. Signed-off-by: Jintack Lim --- arch/arm64/kvm/sys_regs.c | 5 + 1 file changed, 5 insertions(+) diff --git

[RFC PATCH v2 28/38] KVM: arm64: Emulate EL12 register accesses from the virtual EL2

With HCR_EL2.NV bit set, accesses to EL12 registers in the virtual EL2 trap to EL2. Handle those traps just like we do for EL1 registers. One exception is CNTKCTL_EL12. We don't trap on CNTKCTL_EL1 for non-VHE virtual EL2 because we don't have to. However, accessing CNTKCTL_EL12 will trap since

[RFC PATCH v2 36/38] KVM: arm64: Respect virtual HCR_EL2.TVM and TRVM settings

Forward the EL1 virtual memory register traps to the virtual EL2 if they are not coming from the virtual EL2 and the virtual HCR_EL2.TVM or TRVM bit is set. This is for recursive nested virtualization. Signed-off-by: Jintack Lim --- arch/arm64/kvm/sys_regs.c | 24

[RFC PATCH v2 35/38] KVM: arm64: Respect the virtual HCR_EL2.NV bit setting for EL12 register traps

In addition to EL2 register accesses, setting NV bit will also make EL12 register accesses trap to EL2. To emulate this for the virtual EL2, forword traps due to EL12 register accessses to the virtual EL2 if the virtual HCR_EL2.NV bit is set. This is for recursive nested virtualization.

[RFC PATCH v2 30/38] KVM: arm64: Allow the virtual EL2 to access EL2 states without trap

When the virtual E2H bit is set, we can support EL2 register accesses via EL1 registers from the virtual EL2 by doing trap-and-emulate. A better alternative, however, is to allow the virtual EL2 to access EL2 register states without trap. This can be easily achieved by not traping EL1 registers

[RFC PATCH v2 32/38] KVM: arm64: Trap and emulate CPTR_EL2 accesses via CPACR_EL1 from the virtual EL2 with VHE

While the EL1 virtual memory control registers can be accessed in the virtual EL2 with VHE without trap to manuplate the virtual EL2 states, we can't do that for CPTR_EL2 for an unfortunate reason. This is because the top bit of CPTR_EL2, which is TCPAC, will be ignored if it is accessed via

[RFC PATCH v2 33/38] KVM: arm64: Emulate appropriate VM control system registers

Now that the virtual EL2 can access EL2 register states via EL1 registers, we need to consider it when selecting the register to emulate. Signed-off-by: Jintack Lim --- arch/arm64/kvm/sys_regs.c | 46 -- 1 file changed, 44

[PATCH 4/4] iommu/iova: Make dma_32bit_pfn implicit

From: Zhen Lei Now that the cached node optimisation can apply to all allocations, the couple of users which were playing tricks with dma_32bit_pfn in order to benefit from it can stop doing so. Conversely, there is also no need for all the other users to explicitly

[PATCH 2/4] iommu/iova: Optimise the padding calculation

From: Zhen Lei The mask for calculating the padding size doesn't change, so there's no need to recalculate it every loop iteration. Furthermore, Once we've done that, it becomes clear that we don't actually need to calculate a padding size at all - by flipping the

[RFC PATCH v2 31/38] KVM: arm64: Manage the shadow states when virtual E2H bit enabled

When creating the shadow context for the virtual EL2 execution, we can directly copy the EL2 register states to the shadow EL1 register states if the virtual HCR_EL2.E2H bit is set. This is because EL1 and EL2 system register formats compatible with E2H=1. Now that we allow the virtual EL2 modify

[RFC PATCH v2 27/38] KVM: arm64: Add EL2 registers defined in ARMv8.1 to vcpu context

ARMv8.1 added more EL2 registers: TTBR1_EL2, CONTEXTIDR_EL2, and three EL2 virtual timer registers. Add the first two registers to vcpu context and set their handlers. The timer registers and their handlers will be added in a separate patch. Signed-off-by: Jintack Lim ---

[RFC PATCH v2 26/38] KVM: arm64: Add macros to support the virtual EL2 with VHE

These macros will be used to support the virtual EL2 with VHE. Signed-off-by: Jintack Lim --- arch/arm64/include/asm/kvm_emulate.h | 24 1 file changed, 24 insertions(+) diff --git a/arch/arm64/include/asm/kvm_emulate.h

[PATCH 3/4] iommu/iova: Extend rbtree node caching

The cached node mechanism provides a significant performance benefit for allocations using a 32-bit DMA mask, but in the case of non-PCI devices or where the 32-bit space is full, the loss of this benefit can be significant - on large systems there can be many thousands of entries in the tree,

[PATCH] ALSA: hda: constify pci_device_id.

pci_device_id are not supposed to change at runtime. All functions working with pci_device_id provided by work with const pci_device_id. So mark the non-const structs as const. File size before: textdata bss dec hex filename 2610 304 82922 b6a

[PATCH 1/4] iommu/iova: Optimise rbtree searching

From: Zhen Lei Checking the IOVA bounds separately before deciding which direction to continue the search (if necessary) results in redundantly comparing both pfns twice each. GCC can already determine that the final comparison op is redundant and optimise it down to

Re: [RFC PATCH v1 00/11] Create fast idle path for short idle periods

On Tue, Jul 18, 2017 at 09:37:57AM -0700, Arjan van de Ven wrote: > that's just a matter of fixing the C1 and later thresholds to line up right. > shrug that's the most trivial thing to do, it's a number in a table. Well, they represent a physical measure, namely the break-even-time. If you go

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