This patch series enables use Direct access controller on Cadence QSPI
which helps in accessing QSPI flash in memory mapped mode.
On TI platforms, this mode has higher throughput compared to indirect
access mode.
Tested on TI's 66AK2G GP EVM.
It would be great if this patch series could be teste
Hi Dmitry,
On Fri, Dec 29, 2017 at 10:14:27AM +0300, Dmitry Mastykin wrote:
> Module auto-load doesn't work because i2c table is not exported.
>
> Signed-off-by: Dmitry Mastykin
> ---
> drivers/iio/adc/max9611.c | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/dri
Move configuring of indirect read/write start address to
cqspi_indirect_*_execute() function and rename cqspi_indirect_*_setup()
function. This will help to reuse cqspi_indirect_*_setup() function for
supporting direct access mode.
Signed-off-by: Vignesh R
---
v2: No changes.
drivers/mtd/spi-n
On Fri, Dec 29, 2017 at 9:14 AM, Dmitry Mastykin wrote:
> Module auto-load doesn't work because i2c table is not exported.
>
The simplest fix is to move to ->probe_new() since the driver is not
used out of DT/ACPI enumeration.
> Signed-off-by: Dmitry Mastykin
> ---
> drivers/iio/adc/max9611.c
On Thu, Dec 28, 2017 at 12:33:22PM +0300, Alexander Tsoy wrote:
> Hello,
>
> 4.14.9 fails to boot if CONFIG_MCORE2 is enabled and when compiled with
> gcc 6+. More details in the following bug reports:
> https://bugzilla.kernel.org/show_bug.cgi?id=198263
> https://bugs.gentoo.org/642268
>
> I bis
On Thu, Dec 28, 2017 at 11:29:04AM +0530, Naresh Kamboju wrote:
> On 27 December 2017 at 22:15, Greg Kroah-Hartman
> wrote:
> > This is the start of the stable review cycle for the 4.14.10 release.
> > There are 74 patches in this series, all will be posted as a response
> > to this one. If anyon
On Wednesday 27 December 2017 12:15 AM, Trent Piepho wrote:
> On Sun, 2017-12-24 at 05:36 +0100, Cyrille Pitchen wrote:
>> this series tries to solve a long time issue of compatibility between the
>> MTD and SPI sub-systems about whether we should use DMA-safe memory.
>
> Can this should replace
On Thu, Dec 28, 2017 at 10:03:00PM +0530, Naresh Kamboju wrote:
> On 27 December 2017 at 22:16, Greg Kroah-Hartman
> wrote:
> > This is the start of the stable review cycle for the 4.9.73 release.
> > There are 21 patches in this series, all will be posted as a response
> > to this one. If anyone
On Thu, Dec 28, 2017 at 09:39:22AM +0100, Arnd Bergmann wrote:
> On Thu, Dec 28, 2017 at 8:38 AM, Olof's autobuilder wrote:
> > Here are the build results from automated periodic testing.
> >
> > The tree being built was stable-rc, found at:
> >
> > URL:
> > git://git.kernel.org/pub/scm/linux/ker
On Thu, Dec 28, 2017 at 07:42:02AM -0800, Guenter Roeck wrote:
> On 12/27/2017 08:45 AM, Greg Kroah-Hartman wrote:
> > This is the start of the stable review cycle for the 4.14.10 release.
> > There are 74 patches in this series, all will be posted as a response
> > to this one. If anyone has any
Hello,
On (12/29/17 16:26), Minchan Kim wrote:
[..]
> > Gopi Sai Teja, please discuss with Sergey about patch credit.
>
> Hi Gopi Sai Teja,
>
> Now I read previous thread at v1 carefully, I found Sergey already
> sent a patch long time ago which is almost same one I suggested.
> And he told he w
On Thu, Dec 28, 2017 at 03:29:06PM +0200, Stanislav Nijnikov wrote:
> --- /dev/null
> +++ b/drivers/scsi/ufs/ufs-sysfs.c
> @@ -0,0 +1,170 @@
> +/*
> +* UFS Device Management sysfs
> +*
> +* Copyright (C) 2017 Western Digital Corporation
> +*
> +* This program is free software; you can redistribute
Hi,
On Monday 18 December 2017 11:46 PM, Cyrille Pitchen wrote:
> This patch updates the prototype of most handlers from 'struct
> pci_epc_ops' so the EPC library can now support multi-function devices.
>
> Signed-off-by: Cyrille Pitchen
> ---
> drivers/pci/dwc/pcie-designware-ep.c | 2
On Fri, Dec 29, 2017 at 02:08:08AM +0100, Hans-Peter Jansen wrote:
> Hi Greg,
>
> I know, everybody hates NVidia and their proprietary stuff around here.
>
> Anyway, I wanted to let you and followers of 4.14 know, that changes between
> 4.14.8 and 4.14.9 broke both current nvidia kernel drivers.
So we have an entirely new memory model and this is sent after -rc5?
That's not really how things are supposed to work, are they?
/linux/commits/Peng-Fan/ARM-imx-introduce-imx_l2c310_write_sec/20171229-150558
base: https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
for-next
config: arm-arm5 (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget
https
On Thu, Dec 28, 2017 at 09:24:53PM +0100, Pavel Machek wrote:
> On Wed 2017-12-27 23:17:19, Sakari Ailus wrote:
> > On Wed, Dec 27, 2017 at 10:05:43PM +0100, Pavel Machek wrote:
> > > Hi!
> > >
> > > In v4.14, back camera on N900 works. On v4.15-rc1.. it works for few
> > > seconds, but then I get
On Tue, Dec 5, 2017 at 4:17 AM, Andrew Cooks wrote:
> Using TCA6424A with i2c-piix4 bus driver requires byte-at-a-time IO,
> because the i2c-piix4 driver (and probably some SMBus controllers) don't
> support I2C_SMBUS_I2C_BLOCK_DATA.
Why not to fix piix4 for now?
> static int pca953x_write_regs
On 12/29/2017 5:09 PM, Amir Goldstein wrote:
On Fri, Dec 29, 2017 at 3:47 AM, Byungchul Park wrote:
On Wed, Dec 13, 2017 at 03:24:29PM +0900, Byungchul Park wrote:
Lockdep works, based on the following:
(1) Classifying locks properly
(2) Checking relationship between the classes
If (
On Thu, Dec 28, 2017 at 10:42:21PM +0100, Bartosz Golaszewski wrote:
> 2017-12-28 12:28 GMT+01:00 Johan Hovold :
> > On Wed, Dec 27, 2017 at 03:10:38PM +0100, Bartosz Golaszewski wrote:
> >> This function can fail with -EBUSY, but we don't check its return
> >> value in at24_remove(). Bail-out of r
Pickup, Sioh Lee crc32 patch, after some long conversation
and hassles, merge with my work on xxhash, add
choice fastest hash helper.
Base idea are same, replace jhash2 with something faster.
Perf numbers:
Intel(R) Xeon(R) CPU E5-2420 v2 @ 2.20GHz
ksm: crc32c hash() 12081 MB/s
ksm: jhash2 has
This patch implements XDP transmission for TAP. Since we can't create
new queues for TAP during XDP set, exist ptr_ring was reused for
queuing XDP buffers. To differ xdp_buff from sk_buff, TUN_XDP_FLAG
(0x1ULL) was encoded into lowest bit of xpd_buff pointer during
ptr_ring_produce, and was decoded
This patch switches to use ptr_ring instead of skb_array. This will be
used to enqueue different types of pointers by encoding type into
lower bits.
Signed-off-by: Jason Wang
---
drivers/net/tap.c | 41 +
drivers/net/tun.c | 42 ++
Hi all:
This series tries to implement XDP transmission (ndo_xdp_xmit) for
tuntap. Pointer ring was used for queuing both XDP buffers and
sk_buff, this is done by encoding the type into lowest bit of the
pointer and storin XDP metadata in the headroom of XDP buff.
Tests gets 3.05 Mpps when doing
This seems to miss the linux-block list once again. Please include
it in the next resend.
Why do you need the srcu protection? The completion path can never
sleep.
If there is a good reason to keep it please add commment, and
make the srcu variant a separate function only used by drivers that
need it instead of adding the conditional.
On Sat, Dec 16, 2017 at 04:07:23AM -0800, Tejun Heo wrote:
> Note that this makes blk_abort_request() asynchronous - it initiates
> abortion but the actual termination will happen after a short while,
> even when the caller owns the request. AFAICS, SCSI and ATA should be
> fine with that and I th
Hi Christoph,
On Fri, Dec 29, 2017 at 7:18 PM, Christoph Hellwig wrote:
> This frees the dma_direct_* namespace for a generic implementation.
Don't you mean "dma_nommu" not "dma_microblaze" in the subject line?
Thanks,
--
Julian Calaby
Email: julian.cal...@gmail.com
Profile: http://www.googl
On Friday 29 December 2017 12:24 AM, Trent Piepho wrote:
> On Thu, 2017-12-28 at 11:39 +0100, Cyrille Pitchen wrote:
>> Le 26/12/2017 à 20:43, Trent Piepho a écrit :
>> > On Sun, 2017-12-24 at 05:36 +0100, Cyrille Pitchen wrote:
>> > >
>> > > Then the patch adds two hardware capabilities for SPI
On Fri, 2017-12-29 at 00:44 +0100, Maciej S. Szmigiero wrote:
> On 28.12.2017 16:12, Andy Shevchenko wrote:
> > On Fri, 2017-12-22 at 19:58 +0100, Maciej S. Szmigiero wrote:
> > >
> > > + You will need to provide a module parameter "gpios", or
> > > a
> > > + boot-time parameter "gpio_winbond
On 29 December 2017 at 09:18, Greg Kroah-Hartman
wrote:
> On Thu, Dec 28, 2017 at 11:29:04AM +0530, Naresh Kamboju wrote:
>> On 27 December 2017 at 22:15, Greg Kroah-Hartman
>> wrote:
>> > This is the start of the stable review cycle for the 4.14.10 release.
>> > There are 74 patches in this seri
Set current email address to replace previous employers email addresses.
Signed-off-by: Jeffy Chen
---
.mailmap | 1 +
1 file changed, 1 insertion(+)
diff --git a/.mailmap b/.mailmap
index 1469ff0d3f4d..e18cab73e209 100644
--- a/.mailmap
+++ b/.mailmap
@@ -107,6 +107,7 @@ Linus Lüssing
Mac
On 29/12/17 08:18, Christoph Hellwig wrote:
> Almost every architecture supports a direct dma mapping implementation,
> where no iommu is used and the device dma address is a 1:1 mapping to
> the physical address or has a simple linear offset. Currently the
> code for this implementation is most d
On 29/12/17 07:44, Loic Poulain wrote:
> Hi Colin, Bjorn,
>
> On 26 December 2017 at 21:13, Bjorn Andersson
> wrote:
>> On Tue 19 Dec 09:04 PST 2017, Colin King wrote:
>>
>>> From: Colin Ian King
>>>
>>> msg_body.min_ch_time is being assigned twice; remove the redundant
>>> first assignment.
>>>
On Mon, Dec 25, 2017 at 08:54:33PM +0100, Krzysztof Kozlowski wrote:
> Replace GPL license statements with a SPDX license indentifiers (GPL-2.0
> and GPL-2.0+).
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> arch/arm/mach-s3c64xx/crag6410.h | 5 +
> arch/arm/mach-s3c64xx/ma
Add CCI-400 node and control-port on CPUs needed by MCPM (ie SMP).
Signed-off-by: Mylène Josserand
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 41 +++
1 file changed, 41 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.
From: Chen-Yu Tsai
The A80 is a big.LITTLE SoC with 1 cluster of 4 Cortex-A7s and
1 cluster of 4 Cortex-A15s.
This patch adds support to bring up the second cluster and thus all
cores using the common MCPM code. Core/cluster power down has not
been implemented, thus CPU hotplugging and big.LITTL
The ARM architected timers use an offset between their physical and
virtual counters. That offset should be configured by the bootloader
in CNTVOFF.
However, the A83t bootloader fails to do so, and we end up with an
undefined offset (which in our case is random), meaning that each CPU
will have a
Add 3 registers needed for MCPM (ie SMP): prcm, cpucfg and r_cpucfg.
prcm and cpucfg are identical with sun9i-a80. The only difference
is the r_cpucfg that does not exist on sun9i.
Signed-off-by: Mylène Josserand
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 15 +++
1 file changed, 15 inse
Hello everyone,
This is a V2 of my series that adds SMP support for Allwinner sun8i-a83t
with MCPM (Multi-Cluster Power Management).
Based on last linux-next (next-20171222).
Changes since v1:
- Add Chen Yu's patch in my series (see path 01)
- Add new compatibles for prcm and cpucfg regis
Add the support for A83T.
A83T SoC has an additional register than A80 to handle CPU configurations:
R_CPUS_CFG. Information about the register comes from Allwinner's BSP
driver.
An important difference is the Power Off Gating register for clusters
which is BIT(4) in case of SUN9I-A80 and BIT(0) i
Hello,
Many of the x86 pipeline.json files have the brief description "Total
execution stalls" for both CYCLE_ACTIVITY.CYCLES_NO_EXECUTE and
CYCLE_ACTIVITY.STALLS_TOTAL. Should the case for
CYCLE_ACTIVITY.CYCLES_NO_EXECUTE have a brief description that mentions
cycles? Some of the files do have
Hello Corentin,
Le Thu, 28 Dec 2017 21:31:25 +0100,
Corentin Labbe a écrit :
[...]
> Hello
>
> With the .config that you give me in private, everything seems to work.
> But with mine, the stacktrace still happen.
> After some research, this is due to the following code:
> cpumask_set_cpu(get_c
On Thu, 28 Dec 2017, Randy Dunlap wrote:
> It would be good to get this documentation build error patch
> merged into 4.15. Daniel Vetter says that he merged (applied) it.
>
> [PATCH] documentation/gpu/i915: fix docs build error after file rename
> https://marc.info/?l=linux-kernel&m=1512344194
On Fri, Dec 22, 2017 at 06:40:04PM +0800, chen liu wrote:
> 2017-12-22 0:48 GMT+08:00 Charles Keepax :
> > On Tue, Dec 19, 2017 at 02:19:48PM +0800, chen liu wrote:
> >> 2017-12-18 19:55 GMT+08:00 Charles Keepax :
> >> > On Mon, Dec 18, 2017 at 07:32:41PM +0800, chen liu wrote:
> >> > > 2017-12-18
Hi Russell,
2017-12-28 19:46 GMT+01:00 Russell King - ARM Linux :
> On Thu, Dec 28, 2017 at 07:27:39PM +0100, Antoine Tenart wrote:
>> Hi Florian,
>>
>> On Thu, Dec 28, 2017 at 07:02:09AM -0800, Florian Fainelli wrote:
>> > On 12/28/2017 02:05 AM, Antoine Tenart wrote:
>> > > On Thu, Dec 28, 2017
I can confirm now, that that kernel breaks both a desktop (an ThinkPad T440s
i5) and a headless server (i3930) setup. For the server the attached .config
works fine but switching from CONFIG_GENERIC_CPU to CONFIG_MCORE2 legt them
hang at boot w/op any messages. Similar picture at the desktop.
Bo
Hello,
Le Fri, 29 Dec 2017 11:55:01 +0100,
Mylène Josserand a écrit :
> Hello everyone,
>
> This is a V2 of my series that adds SMP support for Allwinner sun8i-a83t
> with MCPM (Multi-Cluster Power Management).
> Based on last linux-next (next-20171222).
>
> Changes since v1:
> - Add Chen
On Tue 26-12-17 21:12:38, Zi Yan wrote:
> On 8 Dec 2017, at 11:15, Michal Hocko wrote:
[...]
> > @@ -1622,7 +1608,6 @@ static int do_pages_move(struct mm_struct *mm,
> > nodemask_t task_nodes,
> > }
> > chunk_node = NUMA_NO_NODE;
> > }
> > - err = 0;
>
> This line ca
On Tue 26-12-17 21:19:35, Zi Yan wrote:
> On 8 Dec 2017, at 11:15, Michal Hocko wrote:
[...]
> > @@ -1394,6 +1390,21 @@ int migrate_pages(struct list_head *from, new_page_t
> > get_new_page,
> >
> > switch(rc) {
> > case -ENOMEM:
> > +
On Fri, Dec 29, 2017 at 12:12:15PM +0100, Marcin Wojtas wrote:
> Hi Russell,
>
> I see that I misspelled your email address, hence the series remained
> unnoticed:
> https://lkml.org/lkml/2017/12/18/216
>
> In terms of the phylink support, I think the most important are:
> * 3/8
> https://lkml.o
"SZ Lin (林上智)" writes:
> This patch adds support for PID 0x9625 of YUGA CLM920-NC5.
>
> YUGA CLM920-NC5 needs to enable QMI_WWAN_QUIRK_DTR before QMI operation.
>
> qmicli -d /dev/cdc-wdm0 -p --dms-get-revision
> [/dev/cdc-wdm0] Device revision retrieved:
> Revision: 'CLM920_NC5-V1 1 [O
From: Markus Elfring
Date: Fri, 29 Dec 2017 12:15:16 +0100
Omit an extra message for a memory allocation failure in this function.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring
---
drivers/pci/setup-bus.c | 4 +---
1 file changed, 1 insertion(+), 3 de
All right, I tried to do some more digging around, in the hope of
getting as close to the source of the problem as I can.
I went back to the very first commit that went astray for me, 2db1f95
(which is the only one actually panicking), and tried to move from its
parent 90ad9e2 (that boots fine) to
This series fixes couple of issues wrt PCIe legacy IRQ handling on
dra7xx platforms.
Tested on DRA74 EVM.
Changes in v2:
* Drop patches related to errata i870 handling. That will be posted
separately later.
* Split INTD IRQ handling into separate patch.
v1: https://lkml.org/lkml/2017/12/1/5
It is possible that more than one legacy IRQ may be set at the same
time, therefore iterate and handle all the pending INTx interrupts
before clearing the status and exiting the IRQ handler. Otherwise, some
interrupts would be lost.
Signed-off-by: Vignesh R
---
drivers/pci/dwc/pci-dra7xx.c | 10
Legacy INTD IRQ handling is broken on dra7xx due to fact that driver
uses hwirq in range of 1-4 for INTA, INTD whereas IRQ domain is of size
4 which is numbered 0-3. Therefore when INTD IRQ line is used with
pci-dra7xx driver following warning is seen:
WARNING: CPU: 0 PID: 1 at kernel/irq/i
On 2017-12-29 11:36, Jeffy Chen wrote:
> Set current email address to replace previous employers email addresses.
>
> Signed-off-by: Jeffy Chen
> ---
>
> .mailmap | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/.mailmap b/.mailmap
> index 1469ff0d3f4d..e18cab73e209 100644
> --- a/.mai
On Wed, 27 Dec 2017 18:47:18 -0800
Ji-Hun Kim wrote:
> Clean up checkpatch warning:
> CHECK: Unnecessary parentheses around 'st->devid != ID_AD7195'
>
> Signed-off-by: Ji-Hun Kim
I've personally never really cared about this particular one as
removing the brackets doesn't make the code easier t
On Thu, 2017-12-28 at 22:59 +0100, Thomas Gleixner wrote:
> On Thu, 28 Dec 2017, Thomas Gleixner wrote:
> > On Thu, 28 Dec 2017, Andy Shevchenko wrote:
> > > The result w/o above is (full log is available here
> > > https://pastebin.com
> > > /J5yaTbM9):
> >
> > Ok. Which irqs are related to that
On Thu, 28 Dec 2017 07:07:17 +0100 (CET)
Julia Lawall wrote:
> On Wed, 27 Dec 2017, Ji-Hun Kim wrote:
>
> > Clean up checkpatch warning:
> > CHECK: spaces preferred around that '-' (ctx:VxV)
> >
> > Signed-off-by: Ji-Hun Kim
> > ---
> > drivers/staging/iio/adc/ad7192.c | 2 +-
> > 1 file chang
Change the previous employers email addresses to the current email address.
Signed-off-by: Jeffy Chen
Acked-by: Martin Kepplinger
---
Changes in v2:
Rewrite commit message.
.mailmap | 1 +
1 file changed, 1 insertion(+)
diff --git a/.mailmap b/.mailmap
index 1469ff0d3f4d..e18cab73e209 100644
On Fri, Dec 29, 2017 at 06:49:15AM -0500, Alexandru Chirvasitu wrote:
> All right, I tried to do some more digging around, in the hope of
> getting as close to the source of the problem as I can.
>
> I went back to the very first commit that went astray for me, 2db1f95
> (which is the only one act
Hi Martin,
Thanks for your reply.
On 12/29/2017 08:04 PM, Martin Kepplinger wrote:
On 2017-12-29 11:36, Jeffy Chen wrote:
Set current email address to replace previous employers email addresses.
Signed-off-by: Jeffy Chen
---
.mailmap | 1 +
1 file changed, 1 insertion(+)
diff --git a/.m
The following commits:
commit f6dd927f34d6 ("[media] media: ov7670: calculate framerate properly for
ov7675")
commit 04ee6d92047e ("[media] media: ov7670: add possibility to bypass pll for
ov7675")
introduced the ability to bypass PLL multiplier and use input clock (xvclk)
as pixel clock output f
Always make sure to CC linux-api mailing list when proposing user
visible API patches.
On Wed 27-12-17 20:30:12, Chao Fan wrote:
> In sometimes users specify the memory region in immovable node in
> some kernel commandline, such as "kernel_core" or the "immovable_mem="
> in the patchset that I hav
Hi Arnd, Olof,
This is the 2nd bug-fix pull request for v4.15.
Just one DT fix. Please pull!
The following changes since commit 50c4c4e268a2d7a3e58ebb698ac74da0de40ae36:
Linux 4.15-rc3 (2017-12-10 17:56:26 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux
On Fri, 29 Dec 2017 18:00:04 +0800
Jason Wang wrote:
> This patch implements XDP transmission for TAP. Since we can't create
> new queues for TAP during XDP set, exist ptr_ring was reused for
> queuing XDP buffers. To differ xdp_buff from sk_buff, TUN_XDP_FLAG
> (0x1ULL) was encoded into lowest b
Eric,
On Thu, Dec 28, 2017 at 9:04 AM, Eric Leblond wrote:
> Signed-off-by: Eric Leblond
> Acked-by: Alexei Starovoitov
> ---
> tools/lib/bpf/bpf.c| 2 ++
> tools/lib/bpf/bpf.h| 2 ++
> tools/lib/bpf/libbpf.c | 2 ++
> tools/lib/bpf/libbpf.h | 2 ++
> 4 files changed, 8 insertions(+)
>
Device-Mapper's "asm-striped" target is used to create a striped (i.e. RAID-0)
device across one or more underlying devices. Data is written in "chunks",
with consecutive chunks rotating among the underlying devices. This can
potentially provide improved I/O throughput by utilizing several physical
The function register_shrinker in ion_heap_init_shrinker may return an
error, check it out. Meanwhile, ion_heap_init_shrinker has to a return
value.
Signed-off-by: Xiongwei Song
---
drivers/staging/android/ion/ion.c | 8 ++--
drivers/staging/android/ion/ion.h | 2 +-
drivers/stagin
From: liuchaowei
The previous stripe index search algorithm use sequential search and
it's very slow if there are many and many physical storage devices.
The new alrogithm save the stripe index into stripe node structure,
and this driver will fetch stripe index from stripe node pointer
directly,
From: liuchaowei
This asymmetric stripe target device driver can achieve better io
performance between those devices which possess different io performance
There are 2 storage device or flash devices: A and B, their sequential
read performance are 220M/s and 315M/s respectively, so their sequent
Hi Mathieu,
On 28.12.2017 22:29, Mathieu Malaterre wrote:
--- /dev/null
+++ b/drivers/nvmem/jz4780-efuse.c
@@ -0,0 +1,305 @@
+/*
+ * JZ4780 EFUSE Memory Support driver
+ *
+ * Copyright (c) 2017 PrasannaKumar Muralidharan
+ *
+ * This program is free software; you can redistribute it and/or mo
Simplify calculation of chip->phy_addr_base in lan9303_detect_phy_setup().
Use GENMASK to calculate phys_mii_mask from LAN9303_NUM_PORTS and
phy_addr_base.
Signed-off-by: Egil Hjelmeland
---
drivers/net/dsa/lan9303-core.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --
Non functional cleanups involving chip->phy_addr_sel_strap.
As promised in https://lkml.org/lkml/2017/11/6/273
Egil Hjelmeland (2):
net: dsa: lan9303: phy_addr_sel_strap rename and retype
net: dsa: lan9303: Adjust phy_addr_base expressions
drivers/net/dsa/lan9303-core.c | 24 ---
chip->phy_addr_sel_strap is declared as a bool, but is also used as an
integer address base.
Rename 'phy_addr_sel_strap' to 'phy_addr_base', and change type to int.
Signed-off-by: Egil Hjelmeland
---
drivers/net/dsa/lan9303-core.c | 20 ++--
include/linux/dsa/lan9303.h| 2 +
On Tue, Dec 26, 2017 at 2:23 PM, Jiaxun Yang wrote:
> To reduce unnecessary license text.
> diff --git a/arch/mips/loongson64/common/cs5536/cs5536_acc.c
> b/arch/mips/loongson64/common/cs5536/cs5536_acc.c
> index ab4d6cc57384..ba0474bb4a3d 100644
> --- a/arch/mips/loongson64/common/cs5536/cs55
Shunqian,
On Fri, Dec 29, 2017 at 8:52 AM, Shunqian Zheng wrote:
> From: Jacob Chen
>
> Add the subdev driver for rockchip isp1.
> --- /dev/null
> +++ b/drivers/media/platform/rockchip/isp1/rkisp1.c
> @@ -0,0 +1,1205 @@
> +/*
> + * Rockchip isp1 driver
> + *
> + * Copyright (C) 2017 Rockchip
* Jia Zhang wrote:
>
>
> 在 2017/12/28 下午8:24, Ingo Molnar 写道:
> >
> > * Jia Zhang wrote:
> >
> >> Instead of blacklisting all types of Broadwell processor when running
> >> a late loading, only BDW-EP (signature 0x406f1, aka family 6, model 79,
> >> stepping 1) with the microcode version le
Jacopo,
On Thu, Dec 28, 2017 at 3:01 PM, Jacopo Mondi wrote:
> Copy the soc_camera based driver in v4l2 sensor driver directory.
> This commit just copies the original file without modifying it.
> No modification to KConfig and Makefile as soc_camera framework
> dependencies need to be removed fi
* Mathieu Malaterre wrote:
> Hi Ingo,
>
> On Thu, Dec 28, 2017 at 1:15 PM, Ingo Molnar wrote:
> >
> > * Mathieu Malaterre wrote:
> >
> >> Fix non-fatal warnings such as:
> >>
> >> kernel/events/ring_buffer.c:116:1: warning: ‘inline’ is not at beginning
> >> of declaration [-Wold-style-declar
On Mon, 25 Dec 2017 16:57:22 +0100
Marc CAPDEVILLE wrote:
> On asus T100, Capella cm3218 chip is implemented as ambiant light
ambient
> sensor. This chip expose an smbus ARA protocol device on standard
> address 0x0c. The chip is not functional before all alerts are
> acknowledged.
> On asus T1
On Thu, 28 Dec 2017 02:19:55 +0100
"Rafael J. Wysocki" wrote:
> On Monday, December 25, 2017 4:57:22 PM CET Marc CAPDEVILLE wrote:
> > On asus T100, Capella cm3218 chip is implemented as ambiant light
> > sensor. This chip expose an smbus ARA protocol device on standard
> > address 0x0c. The chip
Dear Mr Crapouillou-Cercueil-Sir,
On Thu, Dec 28, 2017 at 2:56 PM, Paul Cercueil wrote:
> Add support for the clocks provided by the CGU in the Ingenic JZ4770
> SoC.
> --- /dev/null
> +++ b/drivers/clk/ingenic/jz4770-cgu.c
> @@ -0,0 +1,487 @@
> +/*
> + * JZ4770 SoC CGU driver
> + *
> + * Copyr
On Mon, 25 Dec 2017 16:57:23 +0100
Marc CAPDEVILLE wrote:
> Somme cosmetic cleanup suggested by Peter Meerwald-Stadler.
>
> Macro name :
>MLUX_PER_LUX => CM32181_MLUX_PER_LUX
>
> Constante name :
>als_it_bits => cm32181_als_it_bits
>als_it_value => cm32181_als_it_value
>
> Comment
Dear Peng,
On Thu, Dec 28, 2017 at 10:35 AM, Peng Fan wrote:
> Some PL310 registers could only be wrote in secure world, so
> introduce imx_l2c310_write_sec to support Linux running in
> non-secure world.
> --- /dev/null
> +++ b/include/soc/imx/imx_sip_smc.h
> @@ -0,0 +1,23 @@
> +/*
> + * Copy
This driver will use the TCU (Timer Counter Unit) present on the Ingenic
JZ47xx SoCs to provide the kernel with a clocksource and timers.
Signed-off-by: Paul Cercueil
---
.../devicetree/bindings/timer/ingenic,tcu.txt | 35 +++
drivers/clocksource/Kconfig| 8 +
dri
The TCU (Timer Counter Unit) of the Ingenic JZ47xx SoCs features 8
channels, each one having its own clock, that can be started and
stopped, reparented, and reclocked.
This driver only modifies the bits of the registers of the TCU that are
related to clocks control. It provides one clock per TCU c
This header contains macros for the registers that are present in the
regmap shared by all the drivers related to the TCU (Timer Counter Unit)
of the Ingenic JZ47xx SoCs.
Signed-off-by: Paul Cercueil
---
include/linux/mfd/syscon/ingenic-tcu.h | 53 ++
1 file chang
This simple driver handles the IRQ chip of the TCU
(Timer Counter Unit) of the JZ47xx Ingenic SoCs.
Signed-off-by: Paul Cercueil
---
.../bindings/interrupt-controller/ingenic,tcu.txt | 32 +
drivers/irqchip/Kconfig| 5 +
drivers/irqchip/Makefile
This header provides clock numbers for the ingenic,tcu
DT binding.
Signed-off-by: Paul Cercueil
---
include/dt-bindings/clock/ingenic,tcu.h | 22 ++
1 file changed, 22 insertions(+)
create mode 100644 include/dt-bindings/clock/ingenic,tcu.h
diff --git a/include/dt-bindings/
Add myself as maintainer for the ingenic-tcu-intc interrupt controller
driver, the ingenic-tcu-clocks clock driver, and the ingenic-tcu
clocksource driver.
Signed-off-by: Paul Cercueil
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index a6
Hi,
This patch set introduces three new drivers, which together control the
TCU (Timer/Counter Unit) of Ingenic JZ47xx SoCs.
The ingenic-tcu-intc driver will demultiplex the TCU IRQ interrupts; the
ingenic-tcu-clocks driver will handle the TCU clocks (enable/disable,
reparenting, reclocking); an
On 26 December 2017 at 19:19, Matt Roper wrote:
> On Wed, Dec 20, 2017 at 10:59:57AM +0100, Daniel Vetter wrote:
>> On Tue, Dec 19, 2017 at 03:27:31PM -0800, Dongwon Kim wrote:
>> > I forgot to include this brief information about this patch series.
>> >
>> > This patch series contains the impleme
On Mon, 25 Dec 2017 16:57:21 +0100
Marc CAPDEVILLE wrote:
> This is from rfc by Alan Cox : https://patchwork.ozlabs.org/patch/381773
>
> The idea is as follows (extract from above rfc) :
> - If an adapter knows about its ARA and smbus alerts then the adapter
> creates its own interrupt handler
On Fri 22-12-17 12:45:15, Seth Forshee wrote:
> On Fri, Dec 22, 2017 at 10:12:40AM -0600, Seth Forshee wrote:
> > On Fri, Dec 22, 2017 at 03:49:25PM +0100, Michal Hocko wrote:
> > > On Mon 18-12-17 15:53:20, Michal Hocko wrote:
> > > > On Fri 01-12-17 08:23:27, Seth Forshee wrote:
> > > > > On Mon,
On Fri, 29 Dec 2017, Alexandru Chirvasitu wrote:
> All right, I tried to do some more digging around, in the hope of
> getting as close to the source of the problem as I can.
>
> I went back to the very first commit that went astray for me, 2db1f95
> (which is the only one actually panicking), and
On Fri, 29 Dec 2017, Andy Shevchenko wrote:
> On Thu, 2017-12-28 at 22:59 +0100, Thomas Gleixner wrote:
> > On Thu, 28 Dec 2017, Thomas Gleixner wrote:
> > > On Thu, 28 Dec 2017, Andy Shevchenko wrote:
>
> > > > The result w/o above is (full log is available here
> > > > https://pastebin.com
> >
在 2017/12/29 下午8:48, Ingo Molnar 写道:
>
> * Jia Zhang wrote:
>
>>
>>
>> 在 2017/12/28 下午8:24, Ingo Molnar 写道:
>>>
>>> * Jia Zhang wrote:
>>>
Instead of blacklisting all types of Broadwell processor when running
a late loading, only BDW-EP (signature 0x406f1, aka family 6, model 79,
>>
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