On Tue, Mar 06, 2018 at 02:12:29PM +0100, Arnd Bergmann wrote:
> On Fri, Mar 2, 2018 at 3:37 PM, Jan Glauber wrote:
> > ThunderX1 dual socket has 96 CPUs and ThunderX2 has 224 CPUs.
>
> Are you sure about those numbers? From my counting, I would have expected
> twice that number in both cases: 48
On 2/28/2018 12:04 PM, Oza Pawandeep wrote:
> +struct pcie_port_service_driver *pcie_port_find_service(struct pci_dev *dev,
> + u32 service)
> +{
> + struct pcie_port_service_driver *drv = NULL;
Remove initialization
> + struct portdrv_s
On Tue, Mar 06, 2018 at 01:39:49PM +0100, Javier Martinez Canillas wrote:
> On 03/06/2018 01:17 PM, Jarkko Sakkinen wrote:
> > On Tue, 2018-03-06 at 11:24 +0200, Tomas Winkler wrote:
> >> This series cleans up tpm timeouts setting and handling.
> >>
> >> First motivation was to fix failures coming
Em Tue, Mar 06, 2018 at 01:39:55PM +0100, Thomas Richter escreveu:
> Perf annotate displays function call assembler instructions
> with a right arrow. Hitting enter on this line/instruction
> causes the browser to disassemble this target function and
> show it on the screen. On s390 this results i
Auto-merge for these events was disabled when auto-merging of non-alias
events was disabled in commit 63ce844 (perf stat: Only auto-merge events
that are PMU aliases).
Non-merging of legacy events is preserved:
$ ./perf stat -ag -e cache-misses,cache-misses sleep 1
Performance counter s
This series of patches adds some simple improvements to the way perf stat
handles PMUs that have multiple instances by:
1. Adding glob-like matching in addition to the prefix-based matching
introduced previously (patch 1).
2. Adding the ability to recover the PMU names when printing the events
To simplify creation of events accross multiple instances of the same type
of PMU stat supports two methods for creating multiple events from a single
event specification:
1. A prefix or glob can be used in the PMU name.
2. Aliases, which are listed immediately after the Kernel PMU events
by per
Starting on v4.12 event parsing code for dynamic pmu events already
supports prefix-based matching of multiple pmus when creating dynamic
events. E.g., in a system with the following dynamic pmus:
mypmu_0
mypmu_1
mypmu_2
mypmu_4
passing mypmu// as an event spec will result in the
On 11/16/2016, 07:10 PM, David Howells wrote:
> Here are two sets of patches. Firstly, the first three patches provide a
> blacklist, making the following changes:
...
> Secondly, the remaining patches allow the UEFI database to be used to load
> the system keyrings:
...
> Dave Howells (2):
>
Em Tue, Mar 06, 2018 at 11:13:13AM +0200, Adrian Hunter escreveu:
> Prevent auxtrace_queues__process_index() from queuing AUX area data for
> decoding when the --no-itrace option has been used.
So I'm putting this one both on perf/urgent and on perf/core, the rest
just on perf/core, ok?
- Arnaldo
On 2018/3/6 16:45, Peter Zijlstra wrote:
> On Tue, Mar 06, 2018 at 10:15:10AM +0800, Li, Aubrey wrote:
>> On 2018/3/5 21:53, Peter Zijlstra wrote:
>>> On Mon, Mar 05, 2018 at 02:05:10PM +0100, Rafael J. Wysocki wrote:
On Mon, Mar 5, 2018 at 1:50 PM, Peter Zijlstra
wrote:
> On Mon, M
Am Montag, den 26.02.2018, 07:07 -0800 schrieb Andrey Smirnov:
> Add code that would query and print out bootloader and application
> firmware version info.
>
> Cc: linux-kernel@vger.kernel.org
> Cc: cphe...@gmail.com
> Cc: Lucas Stach
> Cc: Lee Jones
> Cc: Guenter Roeck
> Signed-off-by: Andrey
On 06/03/18 01:57, Rob Herring wrote:
On Thu, Mar 01, 2018 at 10:51:38AM +0100, Amelie Delaunay wrote:
On some boards, especially when vbus supply requires large current,
and the charge pump on the PHY isn't enough, an external vbus power switch
per port may be used.
Add portN_vbus-supply proper
Am Montag, den 26.02.2018, 07:07 -0800 schrieb Andrey Smirnov:
> Convert print_hex_dump() to print_hex_dump_debug() to be able to
> leverage CONFIG_DYNAMIC_DEBUG.
>
> Cc: linux-kernel@vger.kernel.org
> Cc: cphe...@gmail.com
> Cc: Lucas Stach
> Cc: Lee Jones
> Cc: Guenter Roeck
> Signed-off-by:
On Tue, Mar 06, 2018 at 05:52:44AM -0800, Dave Hansen wrote:
> On 03/06/2018 12:54 AM, Kirill A. Shutemov wrote:
> >> Have you measured how slow this is?
> > No, I have not.
>
> It would be handy to do this. I *think* you can do it on normal
> hardware, even if it does not have "real" support for
Em Tue, Mar 06, 2018 at 11:37:36AM +0800, changbin...@intel.com escreveu:
> From: Changbin Du
>
> The thread::shortname only used by sched command, so move it
> to sched private structure.
>
> Signed-off-by: Changbin Du
> ---
> tools/perf/builtin-sched.c | 95
> +++
On Mon 2018-03-05 10:54:16, Miroslav Benes wrote:
> On Fri, 2 Mar 2018, Joe Lawrence wrote:
>
> > On 03/01/2018 05:28 AM, Petr Mladek wrote:
> > > On Thu 2018-02-22 22:00:28, Miroslav Benes wrote:
> > >> On Wed, 21 Feb 2018, Petr Mladek wrote:
> > >>> This patch allows the late initialization.
> >
Am Montag, den 26.02.2018, 07:07 -0800 schrieb Andrey Smirnov:
> Check received frame length _before_ accepting next byte in order to
> avoid incorrectly rejecting payloads that are RAVE_SP_RX_BUFFER_SIZE
> long.
>
> Cc: linux-kernel@vger.kernel.org
> Cc: cphe...@gmail.com
> > Cc: Lucas Stach
> >
On Wed, Feb 28, 2018 at 10:06:14PM +0200, Igor Stoppa wrote:
> + * Encoding of the bitmap tracking the allocations
> + * ---
> + *
> + * The bitmap is composed of units of allocations.
> + *
> + * Each unit of allocation is represented using 2 consecutive
Am Donnerstag, den 01.03.2018, 08:55 -0800 schrieb Andrey Smirnov:
> Add driver that properly handles input event emitted by RAVE SP
> devices.
>
> > Cc: Dmitry Torokhov
> Cc: linux-in...@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> > Cc: Rob Herring
> > Cc: Mark Rutland
> Cc: devicet..
On Tue, Mar 06, 2018 at 02:19:03PM +0100, Mike Rapoport wrote:
> > +/**
> > + * gen_pool_create() - create a new special memory pool
> > + * @min_alloc_order: log base 2 of number of bytes each bitmap entry
> > + * represents
> > + * @nid: node id of the node the pool structure should
Am Donnerstag, den 01.03.2018, 08:55 -0800 schrieb Andrey Smirnov:
> Add Device Tree bindings for RAVE SP input drvier - an MFD cell of
> parent RAVE SP driver (documented in
> Documentation/devicetree/bindings/mfd/zii,rave-sp.txt).
>
> > Cc: Dmitry Torokhov
> Cc: linux-in...@vger.kernel.org
> Cc
Allows querying GPIO direction from the pad config register.
If the pad is not in GPIO mode, return an error.
Signed-off-by: Javier Arteaga
---
This is needed by the drivers for the UP Squared board, an APL-based
platform. (For now, these drivers are out-of-tree.)
An earlier version of this patc
Em Tue, Mar 06, 2018 at 08:53:02AM +0100, Jiri Olsa escreveu:
> On Tue, Mar 06, 2018 at 11:37:35AM +0800, changbin...@intel.com wrote:
> > From: Changbin Du
> >
> > v2:
> > o add a patch to move thread::shortname to thread_runtime
> > o add function perf_sched__process_comm() to process PERF_
Hi Andrey,
On Thu, Mar 1, 2018 at 1:55 PM, Andrey Smirnov wrote:
l
> +++ b/Documentation/devicetree/bindings/input/zii,rave-sp-pwrbutton.txt
> @@ -0,0 +1,24 @@
> +Zodiac Inflight Innovations RAVE Supervisory Processor Power Button Bindings
> +
> +RAVE SP input device is a "MFD cell" device corres
I have applied both patches to for-4.17/elecom.
Thanks,
--
Jiri Kosina
SUSE Labs
On Fri, 2 Mar 2018, Aishwarya Pant wrote:
> Descriptions have been collected from git commit logs.
Applied, thanks.
--
Jiri Kosina
SUSE Labs
On Tue, Mar 06, 2018 at 02:42:43PM +0100, Jonas Gorski wrote:
> On 5 March 2018 at 21:35, Mark Brown wrote:
> > It's exposing more capability information but it's in the "how did this
> > ever work without the fix" range, and I'd worry that this might cause us
> > to do something like start exerc
On Mon, 5 Mar 2018, Gustavo A. R. Silva wrote:
> Assign true or false to boolean variables instead of an integer value.
>
> This issue was detected with the help of Coccinelle.
>
> Signed-off-by: Gustavo A. R. Silva
I've commited this (and the hid-multitouch variant of it as well) to
for-4.17
Hi Jiri,
On Fri, Dec 8, 2017 at 3:29 PM, Benjamin Tissoires
wrote:
> We actually can have the unbind/rebind logic in hid-core.c, leaving
> only the match function in hid-generic.
> This makes hid-generic simpler and the whole logic simpler too.
>
> Signed-off-by: Benjamin Tissoires
> ---
>
> Hi
On 02/23/2018, 07:26 PM, Greg Kroah-Hartman wrote:
> 4.4-stable review patch. If anyone has any objections, please let me know.
>
> --
>
> From: Dan Williams
>
> (cherry picked from commit 2fbd7af5af8665d18bcefae3e9700be07e22b681)
>
> The syscall table base is a user controlle
From: Borislav Petkov
Struct is part of the uapi, document that fact and all fields properly
and fix formatting.
No functionality change.
Signed-off-by: Borislav Petkov
---
arch/x86/include/uapi/asm/mce.h | 52 ++---
1 file changed, 28 insertions(+), 24 del
From: Seunghun Han
The check_interval file in
/sys/devices/system/machinecheck/machinecheck
directory is a global timer value for MCE polling. If it is changed by
one CPU, mce_restart() broadcasts the event to other CPUs to delete
and restart the MCE polling timer and __mcheck_cpu_init_timer(
From: Borislav Petkov
Hi guys,
here are some more RAS fixes. Please queue 1st and 3rd for urgent.
Thx.
Borislav Petkov (1):
x86/MCE: Cleanup and complete struct mce fields definitions
Seunghun Han (1):
x86/MCE: Synchronize sysfs changes
Tony Luck (1):
x86/MCE: Save microcode revision i
From: Tony Luck
Updating microcode used to be relatively rare. Now that it has become
more common we should save the microcode version in a machine check
record to make sure that those people looking at the error have this
important information bundled with the rest of the logged information.
Si
On 06/03/18 16:06, Arnaldo Carvalho de Melo wrote:
> Em Tue, Mar 06, 2018 at 11:13:13AM +0200, Adrian Hunter escreveu:
>> Prevent auxtrace_queues__process_index() from queuing AUX area data for
>> decoding when the --no-itrace option has been used.
>
> So I'm putting this one both on perf/urgent a
On 03/06/2018 02:48 PM, Phil Reid wrote:
On 6/03/2018 16:36, Jan Glauber wrote:
On Tue, Feb 27, 2018 at 01:26:20PM +, George Cherian wrote:
Add support for SMBus alert mechanism to i2c-xlp9xx driver.
The second interrupt is parsed to use for SMBus alert.
The first interrupt is the i2c con
On 03/05/2018 09:30 AM, Troy Kisky wrote:
On 3/3/2018 1:12 PM, Guenter Roeck wrote:
On 03/03/2018 12:48 PM, Guenter Roeck wrote:
On 03/03/2018 11:07 AM, Troy Kisky wrote:
On 3/3/2018 8:32 AM, Guenter Roeck wrote:
Hi,
since v4.15, I get the following runtime warning when running sabrelite ima
On Mon, Mar 05, 2018 at 02:08:59PM +0100, Greg KH wrote:
> I know there is lots more than Android to ARM, but the huge majority by
> quantity is Android.
> What I'm saying here is look at all of the backports that were required
> to get this working in the android tree. It was non-trivial by a l
On 2018/3/6 21:53, Harish Jenny K N wrote:
This patch exports the host capabilities to debugfs
This idea of sharing host capabilities over debugfs
came up from Abbas Raza
Earlier discussions:
https://lkml.org/lkml/2018/3/5/357
https://www.spinics.net/lists/linux-mmc/msg48219.html
Signed-off-by
On Fri, 2018-02-23 at 19:26 +0100, Greg Kroah-Hartman wrote:
> 4.4-stable review patch. If anyone has any objections, please let me know.
>
> --
>
> From: Arnd Bergmann
>
> commit e7c52b84fb18f08ce49b6067ae6285aca79084a8 upstream.
[...]
> --- a/lib/Kconfig.debug
> +++ b/lib/Kco
Normally, ITS device IDs are not shared between different PCIe
devices, and ITS MSIs are allocated from the range that was
reserved when the device's struct its_device was created.
When a duplicate device ID is seen by its_msi_prepare(), it skips
the call to its_create_device(), since it assumes i
On Tue, Mar 6, 2018 at 3:02 PM, Jan Glauber
wrote:
> On Tue, Mar 06, 2018 at 02:12:29PM +0100, Arnd Bergmann wrote:
>> On Fri, Mar 2, 2018 at 3:37 PM, Jan Glauber wrote:
>> > ThunderX1 dual socket has 96 CPUs and ThunderX2 has 224 CPUs.
>>
>> Are you sure about those numbers? From my counting, I
(Fix Andy's Cc: - apologies)
On 06/03/2018 13:42, Javier Arteaga wrote:
> Allows querying GPIO direction from the pad config register.
> If the pad is not in GPIO mode, return an error.
>
> Signed-off-by: Javier Arteaga
> ---
> This is needed by the drivers for the UP Squared board, an APL-based
Em Tue, Mar 06, 2018 at 04:21:32PM +0200, Adrian Hunter escreveu:
> On 06/03/18 16:06, Arnaldo Carvalho de Melo wrote:
> > Em Tue, Mar 06, 2018 at 11:13:13AM +0200, Adrian Hunter escreveu:
> >> Prevent auxtrace_queues__process_index() from queuing AUX area data for
> >> decoding when the --no-itrac
On 03/06/2018 05:29 PM, Ben Hutchings wrote:
> On Fri, 2018-02-23 at 19:26 +0100, Greg Kroah-Hartman wrote:
>> 4.4-stable review patch. If anyone has any objections, please let me know.
>>
>> --
>>
>> From: Arnd Bergmann
>>
>> commit e7c52b84fb18f08ce49b6067ae6285aca79084a8 upst
On Mon, Mar 05, 2018 at 08:44:40PM +0100, Merlijn Wajer wrote:
> Hi Bin,
>
> On 05/03/18 20:28, Bin Liu wrote:
>
> > The musb udc driver sets the state to b_idle without checking a
> > gadget driver, this should be cleaned up. I have add this in my backlog.
> > But if this issue doesn't bother yo
[v9]
* Fixed a rebase issue in Makefile and added Tag from Robh.
[v8]
* Fixed a bug in path#14 pointed out by Viresh and also added tags.
No change in any other patch.
[v7]
* Fixed comments from Viresh for cleaning up the error handling
in qcom-cpufreq.c. Also changed the init funct
From: Stephen Boyd
Krait CPUs have a handful of L2 cache controller registers that
live behind a cp15 based indirection register. First you program
the indirection register (l2cpselr) to point the L2 'window'
register (l2cpdr) at what you want to read/write. Then you
read/write the 'window' regi
From: Stephen Boyd
HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-hfpll.c | 244 +++
drivers/clk/qcom/
From: Stephen Boyd
On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/
From: Stephen Boyd
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-ipq806x.c | 82 ++
1 file changed, 82 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
inde
From: Stephen Boyd
The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these clocks
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 7 +
.../devic
From: Stephen Boyd
The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.
Cc:
Signed-off
From: Stephen Boyd
The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,krait-cc.txt| 22 ++
1
When the Hfplls are reprogrammed during the rate change,
the primary muxes which are sourced from the same hfpll
for higher frequencies, needs to be switched to the 'safe
secondary mux' as the parent for that small window. This
is done by registering a clk notifier for the muxes and
switching to th
In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
that has KRAIT processors the voltage/current value of each OPP
varies based on the silicon variant in use.
operating-points-v2-krait-cpu specifies the phandle to nvmem efuse cells
and the operating-points-v2 table for each opp. The qcom-
On Tue, Mar 6, 2018 at 8:09 AM, Robin Murphy wrote:
> On 06/03/18 01:57, Rob Herring wrote:
>>
>> On Thu, Mar 01, 2018 at 10:51:38AM +0100, Amelie Delaunay wrote:
>>>
>>> On some boards, especially when vbus supply requires large current,
>>> and the charge pump on the PHY isn't enough, an externa
From: Stephen Boyd
Register a cpufreq-generic device whenever we detect that a
"qcom,krait" compatible CPU is present in DT.
Acked-by: Viresh Kumar
[Sricharan: updated to use dev_pm_opp_set_prop_name and
nvmem apis]
Signed-off-by: Sricharan R
Signed-off-by: Stephen Boyd
---
drive
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Kconfig
From: Stephen Boyd
Describe the HFPLLs present on MSM8960 and APQ8064 devices.
Acked-by: Rob Herring (bindings)
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-msm8960.c | 172 +++
include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
2 files changed
From: Stephen Boyd
Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,hfpll.txt | 46 ++
1 file changed, 46 i
Hi Martin
Can you take your precious time to review this ?
Thanks in advice.
Jianchao
On 03/03/2018 09:54 AM, Jianchao Wang wrote:
> In scsi core, __scsi_queue_insert should just put request back on
> the queue and retry using the same command as before. However, for
> blk-mq, scsi_mq_requeue_cm
+Viresh
On Tue, Mar 6, 2018 at 7:05 AM, Amit Kucheria wrote:
> From: Rajendra Nayak
>
> Add cpu cooling maps for cpu passive trip points. The cpu cooling
> device states are mapped to cpufreq based scaling frequencies.
>
> Signed-off-by: Rajendra Nayak
> Signed-off-by: Amit Kucheria
> ---
> a
From: Stephen Boyd
We want to reuse the logic in clk-mux.c for other clock drivers
that don't use readl as register accessors. Fortunately, there
really isn't much to the mux code besides the table indirection
and quirk flags if you assume any bit shifting and masking has
been done already. Pull
Folks,
On Tue, Feb 13, 2018 at 09:05:39AM +0800, Wanpeng Li wrote:
> This patchset introduces dedicated vCPUs(vCPU pinning, and there is no
> vCPU over-commitment) hint KVM_HINTS_DEDICATED, it has two users now:
>
> 1) Waiman Long mentioned that:
>
> Generally speaking, unfair lock performs
Remove unused "type" field from struct exynos_tmu_platform_data.
There should be no functional changes caused by this patch.
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/thermal/samsung/exynos_tmu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/thermal/samsung/exynos_tmu.
All SoCs use the same values (25, 85) for trim points (except
Exynos5440 which currently specifices value 70 for the second trim
point -> it seems to be a mistake because documentation uses value
85 and two points based trimming has never been used by the driver
for this SoC anyway) so just make it
Since pdata efuse values are SoC (not platform) specific just move
them from platform data to struct exynos_tmu_data instance. Then
remove parsing of samsung,tmu[_,min_,max]_efuse_value properties.
There should be no functional changes caused by this patch.
Signed-off-by: Bartlomiej Zolnierkiewic
thermal_exynos.h is used only by exynos_tmu.c so there is no need
for a separate include file. Also while it remove unused defines.
There should be no functional changes caused by this patch.
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/thermal/samsung/exynos_tmu.c | 5 +++--
i
Remove no longer needed samsung thermal properties.
There should be no functional changes caused by this patch.
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/boot/dts/exynos3250.dtsi | 2 +-
arch/arm/boot/dts/exynos4.dtsi | 2 +-
arch/arm/boot/dt
exynos_tmu.h is used only by exynos_tmu.c so there is no need
for a separate include file.
There should be no functional changes caused by this patch.
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/thermal/samsung/exynos_tmu.c | 18 +++-
drivers/thermal/samsung/exynos_tmu.h |
Since pdata gain values are SoC (not platform) specific just move
it from platform data to struct exynos_tmu_data instance. Then
remove parsing of samsung,tmu_gain property.
There should be no functional changes caused by this patch.
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/thermal/
Remove documentation for longer needed samsung thermal properties.
Signed-off-by: Bartlomiej Zolnierkiewicz
---
.../devicetree/bindings/thermal/exynos-thermal.txt | 23 +-
1 file changed, 5 insertions(+), 18 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal
Add support for SMBus alert mechanism to i2c-xlp9xx driver.
The second interrupt is parsed to use for SMBus alert.
The first interrupt is the i2c controller main interrupt.
Signed-off-by: Kamlakant Patel
Signed-off-by: George Cherian
---
drivers/i2c/busses/i2c-xlp9xx.c | 24
Since calibration type for temperature is SoC (not platform) specific
just move it from platform data to struct exynos_tmu_data instance.
Then remove parsing of samsung,tmu_cal_type property. Also remove no
longer needed platform data structure.
There should be no functional changes caused by this
Hi Will
On 03/06/2018 07:44 AM, Will Deacon wrote:
> Hi Shanker,
>
> On Wed, Feb 28, 2018 at 10:14:00PM -0600, Shanker Donthineni wrote:
>> The DCache clean & ICache invalidation requirements for instructions
>> to be data coherence are discoverable through new fields in CTR_EL0.
>> The following
On 2018/3/6 20:48, Harish Jenny K N wrote:
On Tuesday 27 February 2018 05:26 PM, Harish Jenny K N wrote:
This patch exports RCA register to sysfs which will help in
reading the disk identification information.
Signed-off-by: Harish Jenny K N
---
drivers/mmc/core/mmc.c | 2 ++
drivers/mmc/
Since pdata reference_voltage values are SoC (not platform) specific
just move it from platform data to struct exynos_tmu_data instance.
Then remove parsing of samsung,tmu_reference_voltage property.
There should be no functional changes caused by this patch.
Signed-off-by: Bartlomiej Zolnierkiew
All SoCs use the same value (4) for the noise cancel mode so just
make it explicit and remove parsing of samsung,tmu_noise_cancel_mode
property.
There should be no functional changes caused by this patch.
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/thermal/samsung/exynos_tmu.c | 10 +++
Trimming (one point based or two points based) is always used for
the temperature calibration and the default non-trimming code should
never be reached.
Modify temp_to_code() and code_to_temp() accordingly (WARN_ON(1)
in the default cases) and then remove no longer needed parsing of
samsung,tmu_de
Hi,
Values passed through DT properties specific to Exynos thermal
driver ("samsung,*") are SoC (not platform) specific so just
define them in struct exynos_tmu_data instance (or just use
constants where values are identical for all SoCs) and remove
"samsung," DT properties altogether.
The patchs
On Mon, Mar 5, 2018 at 5:55 PM, Benjamin Poirier wrote:
> This reverts commit 19110cfbb34d4af0cdfe14cd243f3b09dc95b013.
> This reverts commit 4110e02eb45ea447ec6f5459c9934de0a273fb91.
> This reverts commit d3604515c9eda464a92e8e67aae82dfe07fe3c98.
>
> Commit 19110cfbb34d ("e1000e: Separate signali
On 06/03/2018 at 20:08:11 +0900, Masahiro Yamada wrote:
> This config select's MFD_SYSCON, but does not depend on HAS_IOMEM.
>
> Compile testing on architecture without HAS_IOMEM causes "unmet
> direct dependencies" in Kconfig phase.
>
> Detected by "make ARCH=score allyesconfig".
>
> Signed-off
On 05/03/2018 at 14:35:58 +0530, Mohit Aggarwal wrote:
> In order to set time in rtc, need to disable
> rtc hw before writing into rtc registers.
>
> Also fixes disabling of alarm while setting
> rtc time.
>
> Signed-off-by: Mohit Aggarwal
> ---
> drivers/rtc/rtc-pm8xxx.c | 49
> ++
On 03/06/2018 03:04 PM, Arnaldo Carvalho de Melo wrote:
> Em Tue, Mar 06, 2018 at 01:39:55PM +0100, Thomas Richter escreveu:
>> Perf annotate displays function call assembler instructions
>> with a right arrow. Hitting enter on this line/instruction
>> causes the browser to disassemble this target
On Mon, Mar 5, 2018 at 5:55 PM, Benjamin Poirier wrote:
> Alex reported the following race condition:
>
> /* link goes up... interrupt... schedule watchdog */
> \ e1000_watchdog_task
> \ e1000e_has_link
> \ hw->mac.ops.check_for_link() ===
> e1000e_check_for_copper_link
>
On Tue, Mar 6, 2018 at 3:33 PM, Andrey Ryabinin wrote:
>
>
> On 03/06/2018 05:29 PM, Ben Hutchings wrote:
>> On Fri, 2018-02-23 at 19:26 +0100, Greg Kroah-Hartman wrote:
>>> 4.4-stable review patch. If anyone has any objections, please let me know.
>>>
>>> --
>>>
>>> From: Arnd Be
On 27/02/2018 at 10:50:03 +0800, Jeffy Chen wrote:
> Since accessing a Chrome OS EC based rtc is a slow operation, there is a
> race window where if the alarm is set for the next second and the second
> ticks over right before calculating the alarm offset.
>
> In this case the current driver is se
On 03/06/2018 12:57 AM, Kirill A. Shutemov wrote:
> On Mon, Mar 05, 2018 at 09:08:53AM -0800, Dave Hansen wrote:
>> On 03/05/2018 08:26 AM, Kirill A. Shutemov wrote:
>>> +static inline bool page_encrypted(struct page *page)
>>> +{
>>> + /* All pages with non-zero KeyID are encrypted */
>>> + re
On Tue, 2018-03-06 at 14:31 +, Javier Arteaga wrote:
> (Fix Andy's Cc: - apologies)
>
> On 06/03/2018 13:42, Javier Arteaga wrote:
> > Allows querying GPIO direction from the pad config register.
> > If the pad is not in GPIO mode, return an error.
> >
> > Signed-off-by: Javier Arteaga
> > -
Hi,
* Tim Harvey [180305 20:59]:
> When acking irqs we need to take into account the ack-invert case.
> Without this chips that require 0's to ACK interrupts will never clear
> the interrupt.
>
> By using regmap_irq_update_bits to ACK the interrupts we use the masked
> status bits so we take car
On Tue, Mar 06, 2018 at 02:56:08PM +, Dave Hansen wrote:
> On 03/06/2018 12:57 AM, Kirill A. Shutemov wrote:
> > On Mon, Mar 05, 2018 at 09:08:53AM -0800, Dave Hansen wrote:
> >> On 03/05/2018 08:26 AM, Kirill A. Shutemov wrote:
> >>> +static inline bool page_encrypted(struct page *page)
> >>>
+CC Mark.
even this is already fixed by a430ab205d29 ("regmap: debugfs:
Disambiguate dummy debugfs file name")
but maybe we can still have this for a better debugfs name?
On 03/06/2018 07:04 PM, Jeffy Chen wrote:
We are now allowing to register debugfs for syscon regmap, and not
having a val
On Tue, 2018-03-06 at 16:56 +0200, Andy Shevchenko wrote:
> On Tue, 2018-03-06 at 14:31 +, Javier Arteaga wrote:
> > > +static int intel_gpio_get_direction(struct gpio_chip *chip,
> > > unsigned int offset)
> > > +{
> > > + if (padcfg0 & PADCFG0_PMODE_MASK)
> > > + return -EINVAL;
>
On 03/06/2018 12:27 AM, Kirill A. Shutemov wrote:
> + anon_vma = page_anon_vma(page);
> + if (anon_vma_encrypted(anon_vma)) {
> + int keyid = anon_vma_keyid(anon_vma);
> + free_encrypt_page(page, keyid, compound_order(page));
> + }
> }
So, just double-checking:
The smsc911x driver will crash if it is rmmod'ed while the netdev
is up like:
Call trace:
phy_detach+0x94/0x150
phy_disconnect+0x40/0x50
smsc911x_stop+0x104/0x128 [smsc911x]
__dev_close_many+0xb4/0x138
dev_close_many+0xbc/0x190
rollback_registered_many+0x140/0x460
rollback_registered
> On 03/06/2018 01:17 PM, Jarkko Sakkinen wrote:
> > On Tue, 2018-03-06 at 11:24 +0200, Tomas Winkler wrote:
> >> This series cleans up tpm timeouts setting and handling.
> >>
> >> First motivation was to fix failures coming from too short timeouts
> >> for commands that creates keys.
> >> Key gene
On Tue, Mar 06, 2018 at 06:59:04AM -0800, Dave Hansen wrote:
> On 03/06/2018 12:27 AM, Kirill A. Shutemov wrote:
> > + anon_vma = page_anon_vma(page);
> > + if (anon_vma_encrypted(anon_vma)) {
> > + int keyid = anon_vma_keyid(anon_vma);
> > + free_encrypt_page(page, keyid, c
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